MIPI C-PHY
MIPI C-PHY IP: three-phase symbol encoding physical layer
Silicon-proven MIPI C-PHY IP, built by Mixel and now part of Silvaco, for IC designers who need CSI-2 camera or DSI display bandwidth on fewer wires.
MIPI C-PHY IP parts by foundry and process
C-PHY pays off when the link has more data to move than pins to move it on. Each trio is three
wires, with no clock lane beside it. Three dedicated parts ship today, all on TSMC. The C-
PHY/D-PHY combo parts cover most other processes.
| Foundry | Product Name | Features | Part Number | Grade |
|---|---|---|---|---|
| TSMC | C-PHY DSI TX in TSMC 22ULL | Supports MIPI C-PHY, 3T, 2.5Gsps | ||
| TSMC | C-PHY DSI RX in TSMC 22ULL | Supports MIPI C-PHY, 3T, 2.5Gsps | ||
| TSMC | C-PHY CSI-2 TX+ in TSMC 40ULP | Supports MIPI C-PHY, 1T, 2.5Gsps, full-speed internal loopback testability |
T means trio, and every rate is per trio. A TX+ part adds full-speed internal loopback with minimal area overhead, so you can test at speed in volume production. Need C-PHY and D-PHY on the same pins? Use a C-PHY/D-PHY combo part, available on TSMC nodes between N2P and 65 nm and on two ST processes. Node not listed? Ask an IP specialist.
Where C-PHY links run
High-bandwidth camera links where lane count is constrained
CSI-2 from image sensor to SoC, carrying as much as 18.24 Gbps on a single trio of three wires.
Display interfaces
SoC out to the panel over DSI, with a transmitter and a receiver both in TSMC 22ULL.
Mobile imaging
Phone cameras and displays, where a combo PHY lets one design talk to C-PHY and D-PHY parts alike.
First to silicon on C-PHY
If C-PHY is new to your roadmap, pick the supplier that took it to silicon first.
That was Mixel. Its founder, Ashraf Takla, now runs mixed-signal IP at Silvaco,
and the team behind that silicon is still with him.
2016
First silicon-proven MIPI C-PHY from any IP provider
2006
Joined the MIPI Alliance, which maintains the C-PHY specification
10 TSMC nodes
TSMC process nodes with silicon-proven Mixel MIPI PHY IP, including N6 and N5
12 nodes · 9 foundries
Process nodes and foundries across Mixel MIPI PHY IP overall
Customer · Mixel MIPI IP (D-PHY)
Summer 2026
indie
indie designs automotive radar processors and MMICs. It licensed Mixel's ASIL-B MIPI D-PHY CSI-2 transmitter and receiver, delivered with certified functional safety work products and a safety manual.
“We needed a MIPI IP provider that could support our strict automotive requirements to further our radar portfolio and enable efficient and scalable ADAS architecture solutions. Through our long-standing partnership with Mixel and their extensive automotive experience, we had full confidence in Mixel's capabilities and reliability. We are looking forward to our continued collaboration.”
Peter Gulden, EVP Radar Systems and Software, indie
Catalog · PDF
March 2026
PRO IP product selection guide
Every C-PHY and C-PHY/D-PHY combo part with its process, grade and part number, next to the rest of Silvaco's production-ready IP.
Press release
March 2026
Mixel MIPI PHY IP available as PRO IP
One to three trios, up to 8.0 Gsps each, built to C-PHY v2.1 and offered as TX, RX, TX+, RX+ and Universal.
Press release
Summer 2026
C-PHY/D-PHY combo IP on TSMC N2P
Mixel's combo IP for TSMC N2P runs 3.0 Gsps per trio of C-PHY v2.1 (6.84 Gbps) and adds D-PHY embedded clock mode on two wires.
Tell us the node and the link
Bring your foundry, your process and the link you’re building, camera or display. An IP
specialist will tell you which C-PHY or combo part fits and how licensing works.
Deliverables come in two parts. Soft views cover the digital control logic: RTL and
STA constraints. Hard views cover the mixed-signal block:
GDSII, CDL, LEF and LIB.
Questions about MIPI C-PHY IP
What is MIPI C-PHY?
MIPI C-PHY is the MIPI physical layer that moves camera and display data as 3-phase symbols on three-wire trios. Its clock is embedded in the symbols, so no separate clock lane is needed. Silvaco's C-PHY IP, built by Mixel, supports v2.1 and works back to v1.1. It carries CSI-2, DSI and DSI-2.
How does C-PHY differ from D-PHY?
D-PHY runs one to four data lanes beside a dedicated clock lane, at up to 6.5 Gbps per lane. C-PHY drops the clock lane and embeds timing in the symbols. It reaches 8.0 Gsps per trio, or 18.24 Gbps. Both carry CSI-2 and DSI. D-PHY is the simpler link, and C-PHY gets more bandwidth out of every wire.
Why does C-PHY use three wires per lane?
Each C-PHY lane is a trio of three wires driven with 3-phase symbol encoding. Every symbol carries 2.28 bits. Timing travels inside the data, so the trio needs no extra wires for a clock. That's how C-PHY gets high throughput from few pins, which matters most when pin count limits your design.
Which parts are available?
Silvaco offers three dedicated C-PHY parts, all at TSMC. In 22ULL there's a DSI transmitter and a matching DSI receiver, both three-trio at 2.5 Gsps. In 40ULP there's a single-trio CSI-2 TX+ at 2.5 Gsps, with full-speed internal loopback for production test. For other processes, check the C-PHY/D-PHY combo parts.
Can C-PHY and D-PHY share an interface?
Yes, with the C-PHY/D-PHY combo IP. It's a dual-mode PHY that runs C-PHY v2.1 on up to three trios or D-PHY v3.5 on up to four lanes. The N2P version supports D-PHY v3.6. Top rates are 8.0 Gsps per trio and 6.5 Gbps per lane. Combo parts run at TSMC from N2P through 65 nm, plus ST 28FDSOI and 40LP.
What data rates are supported?
In high-speed mode, Silvaco's C-PHY IP spans 80 Msps to 8.0 Gsps per trio. That works out to 182.8 Mbps to 18.24 Gbps. Low-power mode runs at 10 Mbps. The three dedicated parts sit at 2.5 Gsps per trio, and the combo Universal part on TSMC 16FFC reaches the full 8.0 Gsps.
Related IP
MIPI
Data lanes beside a forwarded clock, up to 6.5 Gbps per lane, on processes at six foundries.
C-PHY/D-PHY Combo
One PHY for either standard, covering far more processes than the dedicated C-PHY parts.
MIPI IP
D-PHY, C-PHY and M-PHY side by side, so you can choose the physical layer first.