March 1998

The paper describes a generalization of the scanline approach [1] to reconstruction of the shape of planar object represented by a discrete point set with a given distance threshold d.

This article describes a method of reporting DRC errors implemented in Savage, applicable to multi-million transistor layouts. The method of hierarchical information inheritance is a perspective approach in an extension

One of the most challenging and time consuming tasks in VLSI design automation is Layout Versus Schematic (LVS). The problem is to test the consistency between the actual circuit, represented

Q: Is it possible to perform a DRC check on portions rather than on the whole circuit useful when only 2 or 3 errors to fix ?