Testimonials

There are several ways to account for the effect of STI-induced stress in standard compact models. The purpose of this article is to present two different approaches developed by the

In this article, we describe practical behavioral modeling for highly non-linear circuits using Verilog-A, which is analog extension of Verilog-AMS. At first, we describe behavioral modeling techniques for phase/frequency detectors

Q. My simulation fails because SmartSpice cannot find a binned model, what does this mean?

HIPEX-Net is a hierarchical layout extractor. It can create both hierarchical and flat SPICE formatted netlists of the extracted layout. HIPEX-Net also performs ERC (Electric Rule Checking) on the extracted

There is the recent improvement in Expert Layout Editor, the “Shortest path” option was added to Flight line styles (Net Bar). This option allows to build the shortest tree (network)

This article presents an overview of new features added to Silvaco's Expert layout editor. Silvaco has taken a careful look at the real-world obstacles faced daily by semiconductor layout designers

Recent versions of Guardian DRC introduce operations that involve edge layers, either on input or on output. An edge layer is a layer that contains line segments that are edges

We introduce a platform-independent version of Guardian LVS. An important feature of any tool is its capability to operate on various platforms and to support internationalization. Now Guardian LVS is

Q: I have some trouble counting the number of in-stances in a layout using Expert. I have tried to use the Chip Rover feature

Silvaco’s Binary Collision Approximation (BCA) Monte- Carlo Implantation simulator closely replicates the physics of implantation by individually tracking implanted ions and their resulting interstitial and vacancy damage as the ions

This article will present two different ways to extract parasitics from an IC design: first using a full chip extraction tool HIPEX-RC based on geometrical information, then using a field