Shortcode news and reviews
10 years ago
Power integrity issues must be addressed as early in the design cycle as possible to avoid expensive design iterations. Layout engineers can use Silvaco’s InVar Prime to estimate EM, IR
10 years ago
Compared with regular MOSFET devices, the body bias effect in HVMOS is usually more pronounced. In addition to the regular threshold voltage increase with body bias, the LDD region of
10 years ago
3D TFT analysis has been getting lots of attention due to issues caused by 3D effects such as the edge effect on the TFT characteristics. The presence of an enhanced
10 years ago
Dual-Gate Thin Film Transistors (DGTFTs) are often used in pixel driver and peripheral circuits for liquid crystal displays. This is because of the reduction of the gate-off state leakage current
10 years ago
The planar bulk Si metal-oxide semiconductor field-effect transistor (MOSFET) has reached its scaling limit due to various short channel effects (SCE). With 20 nm advanced planar technology, the source and
10 years ago
Parasitic extraction is a mandatory step for physical design sign off, and at advanced nodes, parasitics substantially impact the behavior of circuit design. Any analysis must consider the interconnect parasitic
10 years ago
This webinar will provide specific approaches for simulating electronic device behavioral changes, including oxide charging and physical damage, during their exposure to four of the most common radiation environments that
10 years ago
This webinar will introduce Radiant developed as an integrated simulation environment of LED and OLED devices and will focus on an OLED, which is getting much attention in the field
10 years ago
Semiconductor devices such as bipolar power transistors and solar cells may operate over a range of optical or electrical injection levels. In some cases of high injection, this may result
10 years ago
During the last several years, the enhancement of integrated circuits (ICs) performance and power consumption have contributed to the continual scaling down the size of transistors. However, scaling down semiconductor
10 years ago
Q: How do I extract geometric information, such as material thickness or junction depth, from the current 3D process simulation using Victory Process?
10 years ago
Two-dimensional process simulators based on SUPREM-IV from Stanford University have been used in semiconductor research and industry for almost 30 years. Tremendous progress in the semiconductor technology requires transition to