October 2003

The Input/Output Buffer Information Specification (IBIS) is a standard for electronic behavioral models based on I/V and V/T curve data. It is being developed by the IBIS Open Forum, which

A powerful new feature “Stop-Continue” has been added to SmartSpice to allow the user to suspend a transient simulation and investigate the output before resuming the simulation run from the

Silvaco has always supported the Solaris based Cadence design environment for seemless SmartSpice integration. To accommodate new customer demands to support the new Linux environment, Silvaco has developed a SmartSpice

A new notation has been introduced into SmartSpice to allow a compact expression of a multiple bit wire buss to be used. From this expression the user can simply state