Every software package contains a full set of examples suitable for that version and are installed with the software. If you see examples here that are not in your installation you should consider updating to a later version of the software. These examples can be used by beginners and advanced users for product evaluation, teaching purposes, and self-training.

Required Modules

Victory Process

• 2D Diffusion & Implantation

Victory Mesh:

• 2D Meshing

Victory Device:

• 2D Simulator

This example demonstrates 2D process simulation and basic device tests for a 4H-SiC trench MOSFET.

In the process simulation, after expitaxy to form the n-drift and p-well layers, the trench gate formation is performed by multiple ETCH, DEPOSIT, and oxidation steps. The drift layer doping and thickness are designed for the target breakdown voltage of 1200V, and the well layer doping is designed for the target Vth around 4V. The trench bottom oxide thickness is designed to be thicker so that the maximum electric field at breakdown is less than 10 MV/cm.

Monte Carlo implantation is used to form the n+ and p+ contact regions. Victory Process enables TRAJ.SPLIT and SMOOTH=1 by default, which helps to achieve a smooth doping profile without the formation of isolated n- or p- islands. Such a smooth profile can reduce the risk of convergence problems in the device simulation.

After the process simulation, Victory Mesh is used to generate the appropriate Delaunay mesh for the subsequent device simulation. First, some slices parallel to the SiO2/4H-SiC interface are created by the OFFSET statement. This forces the mesh lines to be aligned parallel to the interface and strongly supports the better representation of the inversion channel behavior. After the REMESH DELAUNAY and several REFINE statements with different modes (Global, Shape, Interface, Junction, and Impurity), the MERGE statement is used to merge the sliced regions with the same material, and then the meshing is completed.

Finally, Victory Device is used to perform two basic device simulations.
-Id-Vg simulation with Vd=0.1 and 10V
-Breakdown simulation

Images