Every software package contains a full set of examples suitable for that version and are installed with the software. If you see examples here that are not in your installation you should consider updating to a later version of the software. These examples can be used by beginners and advanced users for product evaluation, teaching purposes, and self-training.
Required Modules
Victory Process
- 2D Diffusion & Implantation
- 2D Oxidation
Victory Mesh
- 2D Meshing
Victory Device
- 2D Simulator
This example shows how to simulate the full characterisation of a MOS (Part 3):
-Import 1D doping curves into Victory Process
-Transient simulation of gate turn-on
-Drain/Gate Overlap Capacitance
The first part of this example runs a 1D implant simulation and extracts the doping profile. The 1D doping profile is then inserted into the full process simulation. In certain circumstances it is useful to be able to insert doping profiles into process simulations, the profiles may come from any source (such as SRP or SIMS). Here we generate the 1D profile through simulation.
The structure from process simulation, once remeshed and mirrored in Victory Mesh is loaded into Victory Device for a transient simulation of the gate turn-on. The key parts to this are the specification of external RC elements to make an NMOS inverter and the transient solve statement, where structures are saved at certain time points and the time points are appended to the structure file name.
For the RC lumped elements on the CONTACT statement, the external resistance and capacitance are added to the drain electrode. A resistance of 1.0e5 ohms.um is used to correspond to a load resistor in a memory cell. A capacitance of 0.5pF/um is specified to emulate the gates and interconnect the drain must drive. These external elements emulate the formation of an NMOS inverter in SPISCES.
The solve statement for the transient simulation contains the final gate voltage, the ramptime of the gate voltage, the initial timestep, the final simulation time and flags to set the time at which structures are saved at. Only the initial timestep is specified in the solve statement. All other timestep sizes are calculated by Victory Device based on the local truncation error in the solution. It is worth noting that the maximum time step permissible is set and limited by DT.MAX on the method statement, this helps to generate a smoother looking curve.
The final Victory Device simulation is a Gate/drain overlap capacitance extraction using AC analysis. After the initial solution, the gate bias ramped down to -2 volts. Next, the log statement is used to specify a file for saving the results of the gate ramp. Then, the gate is swept from -2 volts to 2 volts in 0.2 volt increments. At each static solution of gate bias the small signal AC response is solved at a frequency of 1 MHz. These results are saved in the log file.
Finally, the transient gate turn-on and the overlap capacitance as a function of gate bias is plotted.
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