Requires: CLEVER Modern designs make use of mask layers which are not always at right angles to each other. The layout used in this example illustrates a 45 degree angle

Requires: CLEVER A useful option included within Clever is its ability to operate in 2D or 1D mode. This greatly reduces simulation time and allows the user to check that

Requires: CLEVER This example demonstrates the use of CLEVER to analyze non planerised structures such as local interconnects commonly used in current sources and in memory cells. To emphasise the

Requires: CLEVER This example demonstrates the ability of CLEVER to deposit and field solve non planarised, multi-layer films for interconnect capacitance analysis using CLEVER. The simulation is run in 2D

Requires: CLEVER This example demonstrates the analytical local oxidation model (LOCOS) included in CLEVER. Oxidation can be included in the process flow to more accurately model the geometry around the

Requires: CLEVER This example is a six-transistor, three metal, single poly SRAM cell. The cell consists of four NMOS and two PMOS transistors. The layout file defines various layers up

Requires: CLEVER, VICTORYPROCESS Minimum Versions: Clever 3.10.13.A, VictoryProcess 7.7.6.A This example creates the same SRAM design as in clex16, but uses the Victory Process simulator to create a more realsitic

Requires: CLEVER We show in this example that CLEVER can be used with a gds2 layout format as input. The commands used are GDS2=”layout.gds” and cell=”cell_number1″ which allow the user

Requires: CLEVER This example illustrates the adaptative meshing capability of CLEVER. You can see the evolution of the mesh refinement using the command: interconnect capacitance AdaptC=0.04 structure=”clex19″. As a result

Requires: CLEVER Micro-loading etching effects describe the phenomenon whereby the effective material etch rate depends on the hole size of the pattern masking layer. This can be simulated using the