Analog Custom Design

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Analog Custom Design

Know how your circuit behaves across process variation before silicon tells you, with Monte Carlo-accurate results up to 30X faster.

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6 years ago

Customer Interview: Why I Rely on SmartSpice

Martin Mallinson is an experienced analog circuit designer with multiple patents. Over his 40-year career, his audio designs have been used in millions of smartphones. Martin spoke with Graham Bell

6 years ago

Simulate 40X Faster with SmartSpice HPP

In this webinar, we describe how SmartSpice HPP takes advantage of the modern multicore hardware platforms to speed up all internal aspects of transient simulations of analog circuits by adopting

6 years ago

Improvement of Parasitic Capacitance Extraction Rules for Large-Scale Layout and Its Accuracy Verification Method

September 17, 2020 | 13:00 – 13:30 (JST) The accuracy of rule-based full-chip parasitic capacitance extraction tools including Silvaco's Hipex is highly dependent on the description of the rule files.

6 years ago

Model Extraction Flow with Utmost IV for Vertically Stacked Nanosheets Using the Leti-NSP Model

July 30, 2020 | 10:00 am – 10:30 am (PDT) This webinar will provide a discussion of common methods used to secure an AMBA-based hardware and software system design.

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6 years ago

Using SmartSpice Compact Models

June 11, 2020 | 10:00 am – 10:30 am (PDT) This webinar will provide a guide to developing Compact Models in SmartSpice to achieve optimal simulation performance. You will learn

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6 years ago

Machine Learning in the EDA-Specific Domain – 20 Years in the Making

June 25, 2020 | 10:00 am – 10:30 am (PDT) This webinar will review these new approaches and how they are applied to different applications. Example ML-based EDA tools form

6 years ago

TFT and OLED SPICE Modeling Using Utmost IV

May 14th 2020 | 10:00 am – 10:30 am (PDT) In this webinar you will learn about SPICE modeling approaches and methods related to flat panel display applications using Silvaco’s

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7 years ago

Silvaco Licenses HiSIM_IGBT Power Device Model Developed by HiSIM Consortium and Provides Support in SmartSpice Circuit Simulator

April 7, 2020

7 years ago

Utmost IV Quick-Start Model Optimization Templates

March 12th 2020 | 10:00 am - 11:00 am (PDT) This webinar will present a new capability available in UTMOST IV: the Quick-Start Optimization Templates. This is a feature that

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7 years ago

Accelerate the Circuit Simulation Flow with Jivaro Parasitic Reduction

Accelerate the Circuit Simulation Flow with Jivaro Parasitic Reduction Jivaro is a unique, stand-alone solution for the reduction of parasitic networks that include resistors, capacitors, and inductors (RLCK). It helps