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Know how your circuit behaves across process variation before silicon tells you, with Monte Carlo-accurate results up to 30X faster.

7 years ago

Accelerate Custom Layout Editing with Expert and JavaScript

Accelerate Custom Layout Editing with Expert and JavaScript Expert is a powerful hierarchical layout editor suitable for a wide variety of design types: Analog, Mixed-Signal, RF, Optoelectronics and Flat Panel

8 years ago

Six-Sigma Analysis of Digital Standard Cells

library of digital standard cells implements both Boolean logic and sequential storage functions. These foundation IPs are used extensively and repeatedly within application specific integrated circuits (ASICs), field programmable arrays

8 years ago

Silicon Creations Relies on Silvaco’s Custom Design Flow for New Advanced FinFET Designs

January 28, 2019

8 years ago

SPICE Model Generation by Machine Learning

by Thomas Blaesi

It was 1988 when I got into SPICE (Simulation Program with Integrated Circuit Emphasis) while I was characterizing a 1.5 μm Standard cell library developed by

Standard Cell Layout Migration and Optimization

Standard Cell Layout Migration and Optimization This webinar will present an efficient methodology for migrating and optimizing standard cell libraries. Foundation IP reuse through migration between non-disruptive technology nodes can

8 years ago

Exploration and Comparison of Various Parasitic Solutions and Parasitic-centric Calculations

Exploration and comparison of various parasitic solutions and parasitic-centric calculations This webinar will provide an overview on methods and tools to review parasitic extractor results and to perform a number

9 years ago

iPDK integration into Gateway Schematic Capture

iPDK integration into Gateway Schematic Capture This webinar will provide a discussion of the integration of iPDK design kits into the Gateway tool flow. iPDKs are fast becoming the prefered

9 years ago

Get a Head Start on Reliability Analysis Early in Your Design Cycle

Get a Head Start on Reliability Analysis Early in Your Design Cycle Power integrity issues must be addressed as early in the design cycle as possible to avoid expensive design

10 years ago

Secrets of Parasitic Extraction Unveiled

Secrets of Parasitic Extraction Unveiled! Parasitic extraction is a mandatory step for physical design sign off, and at advanced nodes, parasitics substantially impact the behavior of circuit design. Any analysis

10 years ago

Power Distribution Network Analysis for Layout Engineers

Power Distribution Network Analysis for Layout Engineers This webinar will provide an overview of Silvaco’s new reliability analysis tool InVar Prime. InVar Prime is an addition to the family of