7 years ago
As semiconductor technology advances, the impact of on-chip variation increases, which means more sophisticated solutions are required.
7 years ago
The Stellar GUI-based field solver tool for parasitic extraction is now integrated into Hipex, Silvaco’s full chip extraction tool. In Hipex, users have a choice of which RC extraction field
7 years ago
In the following video, Dr. Firas Mohamed, VP & GM, Machine Learning & Flow Optimization Division and GM, Silvaco France talks with Graham Bell about Machine Learning technologies deployed in
7 years ago
July 17, 2019
7 years ago
In the following video, I interview Silvaco customer Randy Caplan of Silicon Creations from the show floor at DAC 2019, in Las Vegas, about the latest trends and challenges for
8 years ago
Expert is a powerful hierarchical layout editor suitable for a wide variety of design types: Analog, Mixed-Signal, RF, Optoelectronics and Flat Panel Displays (FPDs). It provides many useful features that
8 years ago
library of digital standard cells implements both Boolean logic and sequential storage functions. These foundation IPs are used extensively and repeatedly within application specific integrated circuits (ASICs), field programmable arrays
8 years ago
January 28, 2019
8 years ago
by Thomas Blaesi
It was 1988 when I got into SPICE (Simulation Program with Integrated Circuit Emphasis) while I was characterizing a 1.5 μm Standard cell library developed by
8 years ago
This webinar will present an efficient methodology for migrating and optimizing standard cell libraries. Foundation IP reuse through migration between non-disruptive technology nodes can save a lot of engineering resources
8 years ago
This webinar will provide an overview on methods and tools to review parasitic extractor results and to perform a number of analyses on the parasitic netlists. Parasitic extraction is an