Gate-all-around nanosheet FETs give 2 nm-and-below nodes the electrostatic control they need, but they also multiply the process and structural parameters your team has to evaluate. Physics-based simulation is accurate, yet its computational cost and specialist setup effort can make it hard to keep pace with real development decisions.
In this webinar, Silvaco demonstrates a complete GAA NSFET FTCO™ (Fab Technology Co-Optimization) workflow, from process simulation of nanosheet formation through device simulation. Victory DoE (Design of Experiments) and Victory Analytics turn a sparse set of high-fidelity simulations into AI-powered surrogate models. You’ll see how those models let teams – beyond simulation specialists – explore trade-offs interactively in real time, before committing to wafer experiments.
Why attend:
- Learn how to build an FTCO™ simulation workflow for GAA NSFET architectures, covering superlattice epitaxy through channel release and gate-all-around formation
- See how smart DoE samples a high-dimensional process parameter space efficiently, and how structural, parametric, and curve surrogates support real-time exploration of process-to-performance trade-offs, including complete Id–Vg characteristics on demand
- Discover how validated surrogates extend simulation insight beyond the simulation specialist group to the wider engineering team
Speaker: Dr. Zhenyu Liu, Sr. Field Application Engineer, Silvaco. Dr. Liu specializes in TCAD process and device simulation for advanced logic CMOS and FTCO, and previously worked in the Research Department of HiSilicon.
Who should attend: Process integration engineers, device engineers, simulation engineers, logic technology development teams, pathfinding engineers, and engineering management.