Concluded event

SURGE Virtual Event Korea 2022

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At a glance

November 10, 2022

Date

Korea

Region

Virtual

Format

12

Sessions in 1 tracks

Silvaco Korea held an online SURGE event on November 10, 2022. You can view the lecture videos below.

SURGE (Silvaco UseRs Global Event) is Silvaco’s global user event where new technologies are introduced and user experiences are shared to explore innovations for advanced semiconductor design.

Date

  • SESSION

Agenda

GENERAL SESSION

SESSION Dr. Babak Taheri – CEO and Board Member – Silvaco, Inc.​

Dr. Babak Taheri, CEO, Board Member,

Dr. Babak Taheri serves as CEO and Board Member of Silvaco, a leading company in TCAD, EDA, and design IP software, and previously served as CTO and Senior Vice President of Product at Silvaco. Prior to Silvaco, he served as CEO and President of IBT, working with investors, private equity firms, and M&A, technology, and business startups.

At IBT, he served as an advisor to MEMS World Summit, Novasentis, AGCM, ALEA Laboratories, Lion Point Capital, and Silver Lake. He also served as Executive Vice President of the Sensor Solutions business unit at Freescale Semiconductor (now NXP).

He received “The Perfect Project Award” from Cypress in 2003 and the “Diamond Chip Award” twice from Freescale in 2013 and 2014. He received the MEMS & Sensors Executive of the Year Award from the UC Davis School of Engineering in 2014 and the Distinguished Engineering Alumni Medal in 2015, and currently serves as an advisor to the UC Davis School of Engineering. Dr. Taheri served on the Governing Board of the ESDA Alliance from 2019 to 2021 and as a director of Parisi House on The Hill from June 2021 to May 2022.

Dr. Babak Taheri has also served as Executive Vice President at Cypress Semiconductors and Invensense (now TDK), and held key positions at SRI International and Apple. He received his Ph.D. in Biomedical Engineering with a major in EECS and Neuroscience from UC Davis. He has published over 20 papers and holds more than 30 patents. In 2021, he published a book titled “Artificial Sensors Shape the Six Pillars of Our Lives.”

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Design and Optimization of Superconducting Circuits – Prof. Giovanni De Micheli, École Polytechnique Fédérale de Lausanne (EPFL), Switzerland

Professor Giovanni De Micheli

Professor Giovanni De Micheli is a professor at the Electrical Engineering Research Institute and Director of the Integrated Systems Center at EPFL in Switzerland.
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Designing Extreme Scale Machine Learning Hardware - Patrick Groeneveld, Ph.D, Cerebras Systems

Dr. Patrick Groeneveld

Dr. Patrick Groeneveld works at Cerebras Systems, a machine learning hardware startup building the world’s first single supercomputer. Dr. Groeneveld has many years of experience in the EDA industry. As a Senior Engineer at Magma Design Automation, he was part of the team that developed the innovative RTL-GDS2 synthesis product. He also served as a full professor of Electrical Engineering at the University of Eindhoven. He currently teaches in the Department of Electrical Engineering at Stanford University and serves as the Finance Chair on the Executive Committee of the Design Automation Conference. He received his Master’s and Ph.D. degrees from Delft University of Technology in the Netherlands.
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TCAD Simulation Update – Dr. Eric Guichard, Silvaco​, Inc.

Dr. Eric Guichard, Senior Vice President, TCAD Division

Dr. Eric Guichard serves as Senior Vice President of TCAD at Silvaco, overseeing the TCAD division from R&D to operational management. Since joining Silvaco in 1995, he has held numerous positions, including Director of Silvaco France and Global Operations Director for the TCAD division. Prior to Silvaco, he worked as a Senior SOI Engineer specializing in transistor and circuit degradation at LETI and Thomson Military and Space. Dr. Eric Guichard obtained a Master’s degree in Materials Engineering and a Ph.D. in Semiconductor Physics from the National Polytechnic University of Grenoble in France.
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Revised Mobility Model for Predictive TCAD Simulations of 4H-SiC – Hemant Dixit, Ph.D., Research Scientist, Wolfspeed, Inc.​

Dr. Hemant Dixit

Dr. Hemant Dixit received his Ph.D. in Physics from the University of Antwerp in Belgium and has over 10 years of experience in the semiconductor industry. Prior to Wolfspeed, he worked at Motorola, IBM, and GLOBAL FOUNDRIES. He is an expert in multi-scale (both atomic and continuum) modeling of semiconductor devices using TCAD tools. Dr. Hemant Dixit has published over 35 research papers cited more than 1,700 times and has filed 15 patent applications (6 granted) with the USPTO. At Wolfspeed, he is dedicated to improving the fundamental understanding of power MOSFETs and to the design and development of next-generation devices.
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Achieving Accurate Experimental Etch Profiles in FinFET and Memory Applications with Victory TCAD Solution – Alexander Toifl, Silvaco, Inc.​

Alexander Toifl, TCAD Development Engineer,

Since joining Silvaco in 2021, Alexander Toifl has been responsible for the etching and deposition models of the Victory Process. He received a Master’s degree in Microelectronics and Photonics and a Ph.D. in Electrical Engineering from the University of Technology Vienna (TU Wien).
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Analog Custom Design Update - Thomas Blaesi, Silvaco, Inc.​

Thomas Blaesi, EDA Vice President

As Vice President of EDA, Thomas F. Blaesi manages the development of all EDA tools, including analog custom design, circuit simulation, and SPICE modeling. He joined Silvaco in October 2017 and served as Vice President of Global Marketing until December 2019. He has over 25 years of experience in corporate strategy, business development, and marketing within the semiconductor and EDA industries. In addition to experience in custom and semi-custom chip design and development, he has led key projects in SoC platform-based design, system-level design, and design for manufacturing.
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A Robust 3nm to 350nm Design Flow Utilizing Silvaco Tools - Chung-Chun Chen, Director of Analog Design, Silicon Creations

Chung-Chun Chen, Director of Analog Design,

Chung-Chun (CC) Chen has been working at Silicon Creations since 2011 and is the Head of Circuit Design for SerDes IO Interfaces. Since 2019, he has led the SerDes team as the Director of Analog/Mixed Signal Design at Silicon Creations in Atlanta, Georgia, USA. From 2018 to 2019, he worked as a driver and designer for Realtek’s high-speed SerDes technology at Ubilinx Technology (Realtek Semiconductor Group) in San Jose, California, USA. From 2011 to 2018, while serving as a Senior Analog Designer and Manager at Silicon Creations in Atlanta, Georgia, USA, he designed analog IP products including Ring-based & LC tank PLLs, Serializers, and De-serializers, along with all clocking components (PLL/CDR, Phase Interpolator) and equalization circuits (FFE, CTLE, DFE). Prior to Silicon Creations, he worked as a researcher at the Samsung Electro-Mechanics Design Center in Atlanta, Georgia, USA. Prior to this, he worked as a senior engineer at TSMC in Taiwan, where he was responsible for cloaking architecture design and related customer support. Chung-Chun (CC) Chen (S’02-M’09-SM’17) was born in Taipei, Taiwan in 1979 and received his Master’s and Ph.D. degrees in Electrical Engineering from National Taipei University in 2004 and 2009, respectively. He currently focuses his research on the circuit design of cloaking and other SerDes components for high-speed communication systems. He has published more than 15 papers in peer-reviewed conferences and journals, and as a senior member of the IEEE, he served as a reviewer for the JSSC and T-MTT.
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Latest Update on Interconnect Parasitic Reduction and Analysis with Jivaro and Viso - Simon-Alexis Abric, Silvaco, Inc.

Simon-Alexis Abric, Silvaco Enterprise Application Engineer

Simon-Alexis Abric is an AE at Silvaco France, responsible for customer technical support for reduction (Jivaro) and parasitic component analysis (Alps) products. Prior to joining Silvaco, he worked as an AE at Edxact SA for four years.

Abric obtained a Master’s degree in Integrated Circuit and Systems Engineering from ENSEIRB in Bordeaux, France in 2013.

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Design IP Solutions Update – Ben Louie, Silvaco, Inc.​

Ben Louie, Foundation IP Associate VP

Ben Louie has over 22 years of experience in memory design, including NOR Flash, NAND Flash, and MRAM. As Director of Memory Design and a Fellow at Spin Memory, he led MRAM memory design work and was one of the key developers of the MRAM Engine IP. Prior to that, he developed new 1T SRAM memory as Director of Design and Senior Design Engineer at Zeno Semiconductor. He also gained experience at startups such as Magsil and Field MRAM IP companies. Additionally, he has worked at major semiconductor companies such as Micron Technology and Xilinx. At Micron Technology, he led the design team for the transition from NOR Flash to NAND Flash and managed the design of the first NAND product. He holds a Bachelor’s and Master’s degree in Electrical Engineering from Santa Clara University and holds over 116 U.S. patents.
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Standard Cells and I/O Library Optimization and Validation - Mr. Faris Amsyar Bin Ahmad Zhaki, IP Staff Engineer, SilTerra Malaysia Sdn. Bhd.

Faris Amsyar Bin Ahmad Zhaki, IP Engineer,

Faris Amsyar Bin Ahmad Zaki is an IP Engineer at SilTerra who has focused on standard cell and I/O library development and silicon verification for over 5 years. Faris Amsyar Bin Ahmad Zaki holds a Bachelor of Science degree in Electronic Engineering from the Malaysian University of Science.
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Cello FinFET Standard Cell Synthesis - Dan Fitzpatrick, Silvaco, Inc.

Dan Fitzpatrick, Associate VP, IP Software Development,

Dan Fitzpatrick serves as Associate VP of IP Software Development at Silvaco Design IP Group in Santa Clara, California, USA, where he leads the development of tools for IP design, characterization, and management. He received his Master of Engineering degree from the University of Florida in Gainesville, Florida, USA.
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Related

SURGE 2023, EMEA

November 21, 2023 · Virtual event

SURGE 2023,
Taiwan/Singapore

November 23, 2023 · Virtual event

SURGE 2023, Japan

November 28, 2023 · Live event

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