SURGE Virtual Event North America 2026

Concluded event

SURGE Virtual Event North America 2026

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At a glance

2026

Date

North America

Region

Virtual

Format

12

Sessions in 4 tracks

Archive Now Available

Silvaco SURGE unites the semiconductor development and design community to explore how Silvaco’s simulation and IP solutions accelerate their R&D and design efforts.

Click on each session or speaker below to learn more.

Date

  • General Session
  • Ramping Manufacturing to Production Using Physics-based Digital Twins Track
  • Enabling Advanced Circuit Designs Track
  • Accelerating Next Generation Power Technologies Track

Agenda

General Session

Why Am I Here?

Wally Rhines, Silvaco, Inc.

Walden C. Rhines, Ph.D., has served as our Chief Executive Officer since August 2025, and as a member of our board of directors since September 2022. From March 2020 to June 2025, Dr. Rhines served as President and Chief Executive Officer of Cornami, Inc., a fabless semiconductor company. Since 2015, Dr. Rhines has also served as a member of the board of directors and as chair of the compensation committee of Qorvo, Inc. (Nasdaq: QRVO), a semiconductor company, since January 2015 and its chairman since November 2023. He served as a member of the board of directors of PTK Acquisition Corp. (NYSE: PTK), a special purpose acquisition company from July 2020 until September 2021 and served on its audit, nominating and compensation committees. From October 1993 to March 2017, Dr. Rhines served as President and Chief Executive Officer of Mentor Graphics Corporation, an EDA company, and chairman of its board of directors from 2000 until its acquisition by Siemens in March 2017, pursuant to which the company was renamed Mentor Graphics, a Siemens Business. Following the acquisition, Dr. Rhines served as President and Chief Executive Officer of Siemens EDA (formerly Mentor Graphics, a Siemens Business), from March 2017 to October 2018, after which he served as its Chief Executive Officer Emeritus until September 2020. Dr. Rhines received a B.S.E. in metallurgical engineering from the University of Michigan, an M.S. and Ph.D. in materials science and engineering from Stanford University, and a M.B.A. from the Southern Methodist University, Cox School of Business.

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Keynote - Memory Innovations: Empowering the AI Revolution to drive Chip Technology Development

Gurtej Sandhu, Micron Technology, Inc.

Gurtej Sandhu is Principal Fellow and Corporate Vice President at Micron Technology. In his current role, he is responsible for Micron’s end-to-end (Si-to-Package) R&D technology roadmaps. The scope includes driving cross-functional alignment across various departments and business units to proactively identifytechnology gaps and ensure resourcing to execute on developing technology solutions. The responsibilities include driving state of the art methodologies to help develop complex technologies faster and more efficiently which entails managing Data and Domain modeling organizations to resource and execute on developing innovative tools for future memory scaling. Dr. Sandhu’s responsibilities also include managing interactions with research consortia around the world.

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Ramping Manufacturing to Production Using Physics-based Digital Twins Track

Ramping Manufacturing to Production Using Physics-based Digital Twins

Garrett Schlenvogt, Silvaco, Inc.

Garrett Schlenvogt, Ph.D., has been Vice President of Worldwide Field Applications Engineering since 2024, overseeing global FAE operations, including technical presales and support. Previously, he served as Director of Worldwide Field Applications Engineering. Since joining Silvaco in 2013, he has held various leadership positions and led research collaborations with academic and commercial institutions. Before Silvaco, he researched radiation and reliability simulation of CMOS technologies for implantable medical devices. Dr. Schlenvogt earned his BSE, MS, and Ph.D. in Electrical Engineering from Arizona State University.
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Unified 3DEXPERIENCE Platform for Accelerating Semiconductor Manufacturing Innovation

Emmanuel Leroux and Morteza Mosheni, Dassault Systèmes

Emmanuel LEROUX
Dassault Systèmes
Emmanuel Leroux is leading the EDA (Electronic Design Automation) strategy for the Simulation Brand (SIMULIA) at Dassault Systèmes. His job, with his Team, is to propose R&D, Partnership to meet a 3Y/6Ytarget for Multi-domain / Multi-scale MODeling and SIMulation (MODSIM) in Electronics involving also manufacturing process simulation. His responsibility includes also more tactical steps and guidance of Go-To-Market and Marketing for the simulation of Semiconductors and PCB (Printed Circuit Boards). Emmanuel received his Ph.D in Electronics in 1998 at University of Lille in France working together with Politecnico di Torino in Italy. In 1994, he joined High Design Technology (Torino) as a PCB Signal Integrity Applications Engineer. In 2020 he joined Computer Simulation Technology (CST), first as Application Engineer (Darmstadt, Germany) and then opening the CST office in Italy. From 2005 he was CST Country Manager for the Southern East Mediterranean area. After the acquisition of CST by Dassault Systèmes in 2016, he led the multi-domain simulation technical/sales Team in that same area. In 2021, he joined Dassault Systèmes SOLIDWORKS Team with the responsibility to launch the Electromagnetic simulation business within SOLIDWORKS resellers at Worldwide level. With his new position Emmanuel has the ambition to plug in EDA MODSIM into a PLM/MBSE/Generative AI framework.

Morteza MOHSENI
Dassault Systèmes
Morteza Mohseni works at Dassault Systèmes SIMULIA as a Roles Portfolio Manager, where he coordinates and contributes to R&D, go-to-market strategy, marketing, and partnership activities to engineer and evolve the SIMULIA brand portfolio within Dassault Systèmes. In this role, he helps to ensure tailored value delivery for semiconductor customers and communities by leveraging market intelligence, close customer engagement, and strategic collaborations. His work supports SIMULIA’s growth objectives, with a particular focus on High-Tech industries and applications in the electronics domain, primarily semiconductors.

He received his PhD from TU Kaiserslautern, Germany, where he worked on the design, simulation, fabrication, and characterization of spintronic-based RF integrated circuits (ICs) and magnetic memories for data processing and data storage systems. He has co-authored more than 30 publications in peer-reviewed journals in the fields of device and applied physics. After a short period of research focused on hardware design for hybrid semiconductor devices for data processing and quantum computing, he transitioned into industry, joining Dassault Systèmes to bridge advanced research with industrial simulation and design workflows.

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Advanced Logic FinFET/Nanosheet Simulation with Silvaco Victory Tools

Zhenhua Wu，Zhejiang University

Zhenhua Wu is a professor with the Zhejiang University. He received his Ph.D. degree in Chinese Academy of Sciences, Beijing, China, in 2011. He joined Semiconductor Research and Development Center, Samsung Electronics, Suwon, South Korea, from 2011 to 2016, and then joined the Institute of Microelectronics, Chinese Academy of Sciences. In 2024, he joined the Center for quantum matters, Zhejiang University, Hangzhou, China. His current research interests include advanced semiconductor manufacturing technology, quantum transport simulation of nanoscale transistors and AI-Augmented TCAD simulation method. His works have been published in IEEE EDL/TED, PRL/PRB/PRApplied, APL/JAP, Nat.Mat/Comm etc., or presented EDTM/SISPAD/IEDM/VLSI etc., conferences. In 2024, He was listed among Elsevier’s top-2 % scientists worldwide.
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Enabling Advanced Circuit Designs Track

Practical Considerations for Developing Usable, Scalable, and Competitive Foundation IP for Foundry Enablement

Keith Odland, Silvaco, Inc.

Keith brings over 30 years of systems-level semiconductor experience to the organization. He leads platform definition and development strategy as part of the leadership team. Before joining Silvaco, Keith held senior leadership roles at indie Semiconductor, Ambiq Micro, Cirrus Logic, and Silicon Laboratories. Keith earned a BSEE from UT Austin’s Cockrell School of Engineering and holds six US patents.
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Accelerating Standard Cell Migration with Silvaco CellForge 2D: DRC Cleanup and Layout Optimization Across Architectures

Navneet Jain, GlobalFoundries, Inc.

Navneet Jain is a Distinguished Member Technical Staff at GlobalFoundries, Inc, Santa Clara, since 2009. He holds a PhD and MTech in EE form IIT Delhi, India and BE(Hons) in EEE from BITS Pilani, India. He has over 25 years of experience in the field of circuit/logic design, optimization and methodologies for timing closures for microprocessors and graphics chip design at SGI, Transmeta, AMD, SGI, Software &Technologies (Duet) and Center for Applied Research in Electronics (CARE) at IIT Delhi. At GlobalFoundries he has architected and productized standard cells libraries in 22FDX, 12LPP, 45SPCLO, RF SOI, Bulk CMOS, and SiGe including several test chips for FAB silicon validations with emphasis on developing ultra-lower and low leakage design. Navneet has over 30 patents and 10 publications in IEEE transactions and international conferences. He is designated as Master Inventor and also a recipient of the CEO award at GlobalFoundries
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Teradyne Thrives in the AI age by Optimizing ASIC Development and System Architecture

Jason Messier, Teradyne, Inc.

With over 25 years of experience in the Semiconductor and Automatic Test Equipment (ATE) industries, Jason Messier is a seasoned technologist currently serving as Director of Silicon Strategy and Technology at Teradyne. Recognized for his transparent leadership style and passion for technically elegant solutions to emerging market needs, Jason contributes thought leadership through identification, organizational championship, and product ownership of novel ATE concepts and initiatives. Previous roles at Analog Devices, Intersil, and semiconductor startups reflect deep experience in product definition, mixed-signal IC design, and customer-focused solutions, leading to multiple successful well-differentiated product launches. Jason holds a BSEE from Northeastern, an MSEE from Carnegie Mellon University, and an MBA from Babson College.
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Curvilinear OPC Applications​

Nobue Kosa, Micron​

N. Kosa received a Bachelor of Science in Electrical Engineering from the University of California, Davis, in 1996. She joined NEC in 1996 as a photo engineer. In 2000, she transferred to Elpida Memory Inc. In 2014, she joined Micron Memory Japan and began working on OPC. She is currently a Member of Technical Staff in the Advanced Mask Development, Recipe, and Tool Development team.

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Accelerating Next Generation Power Technologies Track

Accelerating Next Generation Power Technologies

Britt Brooks, Silvaco, Inc.

Britt has been at Silvaco since November 2024. He is an FAE for Power devices. Britt started his career at Texas Instruments and was a compact modeling engineer for 25+ years and an IC modeling engineer working as factory support for the FAE teams for 6 years. He was the first chairman of the Compact Model Council (now Coalition) for 7 years. Britt came to Silvaco after 4 years at Wolfspeed in the R&D team, working on scaling and predictive modeling of SiC Power MOSFETs. Additional support activities for internal corner modeling and external modeling questions for both discrete and module products were also his responsibility.
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TCAD-Driven Development of Next-Generation Vertical GaN Power Devices

Marc Gensch, Fraunhofer ISIT

Marc Gensch is a Research Associate and Project Leader at Fraunhofer ISIT within the Advanced Devices Group. He holds a B.Sc. and M.Sc. in Physics from the University of Hamburg and earned his doctorate at the Technical University of Munich in cooperation with DESY. Marc’s work focuses on integrating ferroelectric AlScN layers into innovative device architectures, as well as advancing GaN HEMT and vertical GaN device development. At Fraunhofer ISIT, he leads projects such as VerGaN and PowerCare and contributes to initiatives like NeuroSmart & Scaling and APECS, driving progress in next-generation semiconductor technologies.
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Silicon’s Enduring Edge: Advanced SuperQ Power Device Development and Interface Trap Extraction Using SILVACO TCAD

Stan Soloviev, Ideal Semiconductor

Stanislav I. Soloviev, PhD, is a Senior Device Engineer specializing in semiconductor device design, process integration, and material characterization. He has significantly advanced charge-balanced structures and edge termination techniques for high-voltage power devices. His expertise encompasses failure mode effects analysis, root-cause identification, and yield improvement in high-volume manufacturing. Dr. Soloviev earned his PhD in Electrical Engineering from Taganrog Institute of Technology and has authored over 50 peer-reviewed publications and holds 10 patents
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Using Victory 3D Simulation in 375V Partial SOI SJ LDNMOS Breakdown Voltage Study

Dr. Elizabeth Kho Ching Tee, X-FAB

Dr. Elizabeth Kho Ching Tee has nearly two decades of experience in power semiconductor device research and development. She has led major advancements in Superjunction and partial SOI technologies and contributed to the development of integrated power devices, including lateral IGBTs, RESURF LDMOS, and Superjunction LDMOS on PSOI. More recently, she has expanded her work into SiC MOS devices. Dr Elizabeth holds five patents and has authored 18 publications in leading journals and conferences.
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