Every software package contains a full set of examples suitable for that version and are installed with the software. If you see examples here that are not in your installation you should consider updating to a later version of the software. These examples can be used by beginners and advanced users for product evaluation, teaching purposes, and self-training.
Required Modules
Victory Process
- 2D Diffusion & Implantation
- 2D Oxidation
Victory Mesh:
- 2D Meshing
- 2D Solid Modeling
Victory Device:
- 2D Simulator
This example demonstrates 2D process and device simulation of a 4H-SiC double-trench MOSFET, which is one of the promising next-generation candidates [1].
The process starts with the epitaxy of n-drift and p-well layers on a highly n-type doped 4H-SiC substrate. This is followed by the formation of the double trench, which consists of a gate trench and a source trench. P+ implantation takes place inside the source trench and then acts as gate oxide protection under high drain bias voltage. Monte Carlo implantation is used to create n+ and p+ regions. Victory Process enables TRAJ.SPLIT and SMOOTH=1 by default, which helps to achieve a smooth pn junction shape. Trajectory replication (TRAJ.REP) is also used in this example to optimize the simulation time. Once the double trench is formed, activation annealing and electrode formation are performed, completing the process simulation.
After the process simulation, the structure is remeshed to be ready for device simulation using a conformal refinement scheme starting with SIMPLEX.MINIMAL on the REMESH statement. This scheme can also use the OFFSET function to realize mesh lines parallel to the trench MOS interface. Shape, interface, junction, and impurity refinements are performed, followed by the MERGE statement to merge the regions separated by the OFFSET function, thus completing the remeshing.
Moving on to device simulation, a range of SiC specific models are used. The area (WIDTH) is chosen to be typical of a 26A device. The first simulation is for the threshold voltage at the drain voltage of 10V. Two INTTRAP statements are used here to reproduce the gradual increase in drain current at Vg > +4 V often observed in commercial SiC MOSFET products. Then the Id-Vds simulations are performed with Vgs=+6, +8, +10, +12 V, and the Rds(on) vs. Vgs curve is obtained at a constant drain current of 12 A. Finally the off-state breakdown simulation is performed in 128-bit mode, using the OKUTO impact ionization model parameter set proposed by Niwa [2].
References
[1] “Trench Warfare: A SiC Battleground, ” https://www.pgcconsultancy.com/post/trench-warfare-a-sic-battleground
[2] H.Niwa et al., IEEE Transactions on Electron Devices, Vol. 62, No. 10 (2015).
Images
