Every software package contains a full set of examples suitable for that version and are installed with the software. If you see examples here that are not in your installation you should consider updating to a later version of the software. These examples can be used by beginners and advanced users for product evaluation, teaching purposes, and self-training.

Required Modules

Victory Process

• 2D Diffusion & Implantation

Victory Mesh

• 2D Meshing

Victory Device

• 2D Simulator

In this example, a pseudomorphic HEMT structure based on the GaAs-AlGaAs-InGaAs material system is constructed using Victory Process. The structure is then passed to Victory Mesh for device remeshing, and then Victory Device performs device simulations for electrical testing. The input file consists of the following main parts:

-Construction of the device in Victory Process
-Electrical simulation of a family of Id/Vds curves
-Simulation of Id/Vgs characteristics
-Extraction of basic parameters

Since the structure under consideration is non-planar with a non-rectangular recessed gate, it was created in Victory Process, where the HEMT geometry, material regions, doping profiles, and electrodes are defined.

The device is based on a GaAs substrate. It employs a double channel HEMT concept where the InGaAs channel is sandwiched between two AlGaAs regions. The structure also employs 2 delta (or pulse) dopings above and below the channel in both AlGaAs regions. These are modeled by thin 10 angstrom thick layers. The delta doping, usually expressed in terms of planar concentration (cm-2), must be recalculated to bulk doping (cm-3) given the thickness of the layers. SEPARATE.LAYERS in the INIT statement separates these thin layers from neighbouring AlGaAs layers with the same Al composition.

Delta doped regions play an important role in HEMT technologies. They are used to provide additional carriers to the channel and to better control the threshold voltage and other device parameters. The source and drain cap regions are made of GaAs. In practical applications, the source and drain contact alloys often penetrate deep into the structure, well below the channel. This is modelled by heavily doped regions below the source and drain.

The composition fractions of AlGaAs (0.22 for Al) and InGaAs (0.78 for Ga) are specified in Victory Process as the respective region attributes.

The constructed structure is passed to Victory MESH for conformal remeshing. SEPARATE in the LOAD statement specifies that the same material layers should be kept separate.

The Victory Device simulation begins by reading in the structure from Victory Mesh. The first statements specify the material and physical model definitions. The INTERFACE S.S statement activates the thermionic emission model for carrier transport across the heterointerfaces. The material parameters and physical models are specified by the MATERIAL and MODELS statements, respectively. Shockley-Read-Hall recombination, low-field doping-dependent mobility, and electric-field-dependent mobility models are applied to all the materials/regions. The band alignment is set by the ALIGN parameter in the MATERIAL statements, which defines the fraction of the bandgap difference applied to the conduction band. The gate work function is set up in the CONTACT statement.

The simulation is first performed to obtain the state of the structure for 3 different gate biases, Vgs=0, -0.2, and -0.4 V, with the source and drain grounded. The corresponding states of the structure are stored in three separate solution files. The family of three Id-Vds characteristics is calculated in four separate drain voltage sweeps from 0.001 up to 2 V. Each series of the drain biases is performed after loading the solutions with the respective gate bias. The Id-Vds characteristics are stored in three separate log files. The final conditions of the structure with 2V on the drain are also stored in separate solution files. The zero bias condition is reloaded and the Id-Vgs characteristic is calculated. A small-signal AC analysis at 1MHz is also performed during this gate bias sweep.

At the end of the simulation, the following parameters are used to extracted using the EXTRACT function of DeckBuild:
-Threshold voltage (Vth)
-Maximum saturation current (Idss)
-Gate voltage at Id=0.3*Idss
-Maximum gate-source capacitance (Cgs_max)
-Gate-source capacitance at Vg=0
-Gate-source capacitance at Id=0.3Idss
-Maximum transconductance (Gm_max)
-Transconductance at Id=0.3Idss

The results are also displayed using Victory Visual:
-Electron concentration distribution at the zero-bias.
-Id/Vds and Id/Vgs characteristics

Images