Every software package contains a full set of examples suitable for that version and are installed with the software. If you see examples here that are not in your installation you should consider updating to a later version of the software. These examples can be used by beginners and advanced users for product evaluation, teaching purposes, and self-training.

Required Modules

Victory Process:

• Core Simulator

Victory Mesh:

• 2D Meshing

Victory Device:

• 2D Simulator
• 2D TFT

This example demonstrates how integrated process and device TFT simulations can be performed in Victory Process, Victory Mesh, and Victory Device. The input files consist of:

Construction of TFT device in Victory Process

Vgs sweep in Victory Device

The first part of the file uses Victory Process to construct the geometry and doping of a TFT device. The starting substrate is defined as silicon dioxide to emulate the flat panel display glass. The transistor is simulated with a metal gate on the bottom and a gate insulator made from Oxide and Nitride. A lightly doped Silicon layer is deposited to act as the channel region. A heavily doped layer is placed on top to become the source/drain regions. Single crystal Silicon or Polysilicon could be used equally well at this stage. However, the important electrical properties of the material are set in Victory Device, so at this stage it is not important which material is used. Metal for the source/drain contacts is then applied. An etch-back through the metal and heavily doped silicon is then carried out. Some of the lightly doped silicon layer is also removed. This final etch separates the source and drain. The final stage in Victory Process is to define the electrodes for use in Victory Device.

The Victory Device part of this file is used to simulate the gate voltage bias from -10V to +20V with the drain at +10V. Before the biasing is applied it is first necessary to set all the relevant material parameters.

In simulating TFTs, the most important requirement is setting of the defects statement specifying the density of states in the semiconductor bandgap. The defect states are specified as donor-like and acceptor-like and as tail and mid-gap Gaussian states. This gives a total of four distributions each with their own trapping cross sections for electrons and holes for a total of eight cross section values. The values included in this example are typical of amorphous silicon used in TFT transistors, but each user has a different process. The defect densities are sensitive to the hydrogen annealing of the device and so must be tuned by the user.

The material statement is used to set the material constants of the semiconductor to those of amorphous silicon. The interface statement defines an interface charge on each semiconductor/insulator interface. It is possible to vary this charge by position using the bounding box parameters on the interface statement.

The models needed for TFT simulation are simple. A constant mobility as defined by the material statement is used and SRH recombination is included. In order to simulate reverse leakage, the band-band tunnelling model is included by: models bbt.kl. The exponential parameter of the band-band tunnelling model is adjusted for amorphous silicon.

The first step in the solve sequence is to ramp the drain voltage up to +10V. At this point a file is stored. The reverse gate voltage ramp is then applied. The gate voltage is ramped up to -10V. The drain current will increase during this ramp due to tunnelling current in the TFT. The magnitude of this is controlled by the parameters of the band-band tunnelling model. at the end of the ramp the final drain current is extracted.

At the highest reverse gate bias a structure file is saved. By plotting the recombination in the device at this bias it is possible to see the band-band generation current as a negative recombination term.
The final step is the forward gate voltage sweep. This is performed by first loading the solution saved with -10V gate voltage. Then the gate is ramped to +20V. From this data the extract syntax is used to get the sub-threshold leakage slope. This slope, which is typically 0.5-1.5 V/decade is sensitive to the defect distribution in the semiconductor.

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