Every software package contains a full set of examples suitable for that version and are installed with the software. If you see examples here that are not in your installation you should consider updating to a later version of the software. These examples can be used by beginners and advanced users for product evaluation, teaching purposes, and self-training.

Required Modules

Victory Device

• 2D Simulator

This is a demonstration of the hot carrier reliability feature of Victory Device. A PMOS transistor is stressed at high voltages and a threshold voltage shift observed.

The simulation shows:

Formation of PMOS transistor using Victory Device syntax

Id/Vgs test

High voltage stress for 1000 seconds

Id/Vgs tests of devices at various stress times.

The example file consists of five separate Victory Device runs. The first run uses the Victory Device syntax to construct the geometry, mesh and doping of a PMOS transistor. The doping is specified using gaussian functions. The mesh file saved by this run is loaded into the next run.

The second Victory Device run sets commands to perform an Id/Vgs simulation to observe the threshold voltage and gain.

The device degradation modeling is performed in the third run. First, the structure is loaded and the correct workfunction and interface fixed charge are set. On the models statement, the standard mobility and recombination models are specified. The parameters hei, devdeg.e are also set. The hei parameter turns on the hot electron injection model for gate current. The devdeg.e parameter sets that the gate current is used to calculate device degradation. The degradation parameter is used to specify the interface state density and the electron trapping cross section, sigmae. The density of interface states as a function of position is defined here using a C-INTERPRETER routine. This file will be copied to your current working directory if you press ‘Load’. This file contains a C language description of the density of acceptor-like traps at the oxide/silicon interface. Use of the C-INTERPRETER allows complete flexibility in specifying the position of the traps.

The stressing conditions are Vds=-6.0V and Vgs=-1.5V. The device is biased to these voltages in DC mode. Victory Device is then switched to a transient solution. The transient simulation is set to run for 1000s. At various intervals, data is saved to solution files. The statement output devdeg is required to save the interface trap occupancy to these solution files. These files will be the initial starting points of the subsequent Id/Vgs runs.

The fourth and fifth runs are just repetitions of the second one. They perform the Id/Vgs test to observe threshold voltage and gain. However, the important difference is the the file loaded in the mesh statement is the output files saved during the transient stress.

The Id/Vgs curves are overlayed to show the threshold voltage shift caused by the hot carriers trapped at the interface.

Images