Concluded event

SURGE Virtual Event EMEA 2025

EMEA · Tuesday, January 21, 2025 · Virtual event

At a glance

January 21, 2025

Date

EMEA

Region

Virtual

Format

19

Sessions in 3 tracks

About this event

SURGE EMEA 2025 was a single online day, Tuesday, January 21, 2025. Its 20 talks ran from quantum transport in 5nm nanowire transistors to the CAN XL automotive bus.

SURGE is the event Silvaco organizes for its own users. In EMEA, three companies brought results from their own work: Ciena on quantum transport, SilTerra on library characterization and Silicon Creations on parasitic reduction. Stanford and TU Wien added the academic side. Silvaco’s side of the program covered the CEO keynote and engineering updates across TCAD, EDA and IP. Board member Wally Rhines spoke on AI in EDA.

Tracks

Agenda

Recordings for all 20 SURGE North America 2025 talks sit on Silvaco’s support site. To open
one, sign in there or complete a short form with a work, university or government email.

General Session

公司最新进展

Babak Taheri 博士,Silvaco,CEO及董事会成员

He has led Silvaco as CEO since August 2019, stepping away only from September to November 2021. Before that he was CEO of Integrated Biosensing Technologies, an advisory firm, and earlier held roles at Invensense, SRI International and Apple. He sits on the board of Sunright Limited. PhD in biomedical engineering from UC Davis.

人工智能如何将EDA推向新高度

Wally Rhines,Cornami 总裁及CEO、Silvaco董事会成员

He was CEO of Mentor Graphics from 1993 until Siemens acquired it in 2017. He now runs Cornami and chairs the board of Qorvo, and he has served on Silvaco’s board and audit committee since September 2022. Stanford PhD in materials science and engineering.

半导体工艺和器件分会场

Keynote

Dr. Eric Guichard, SVP and GM of TCAD Business Unit, Silvaco

The state of the Victory TCAD simulators, the part TCAD plays while a new device is still in development, and Silvaco’s plans for TCAD from here.
He has run TCAD at Silvaco since November 2012, after four years as VP of Applications. His Silvaco career began in 1995 at Silvaco SA (formerly Silvaco Data Systems). He holds an MS in materials science and a PhD in semiconductor physics, both from Grenoble.

Products: TCAD

AI Takes EDA to the Next Level

Wally Rhines, President and CEO of Cornami and Silvaco Board Member

Recordings for all 20 SURGE North America 2025 talks sit on Silvaco’s support site. To open
one, sign in there or complete a short form with a work, university or government email.

Semiconductor Process and Device Track (TCAD)

TCAD Update

Dr. Eric Guichard, SVP and GM of TCAD Business Unit, Silvaco

The state of the Victory TCAD simulators, the part TCAD plays while a new device is still in development, and Silvaco’s plans for TCAD from here.
He has run TCAD at Silvaco since November 2012, after four years as VP of Applications. His Silvaco career began in 1995 at Silvaco SA (formerly Silvaco Data Systems). He holds an MS in materials science and a PhD in semiconductor physics, both from Grenoble.

Products: TCAD

NanoHub Workforce Development

Dr. Peter Griffin, Stanford University

His work sits where semiconductor fabrication meets bioengineering. He has been lead author on DARPA, NIH and SRC grants, and at Stanford he measures impedance for diagnostic use in Prof. Lars Steinmetz’s lab. With Jim Plummer, he wrote a widely used microfabrication textbook (Cambridge University Press, 2024).

Products: Jivaro Pro

Low-temperature Behavior in Nanowire Transistors by Quantum Transport Simulation

Sanam Moslemi-Tabrizi, Analog Engineer, Ciena

Supplied device models lose accuracy as Ciena’s analog designs shrink, because quantum effects that classical simulators can’t capture start to dominate. Ciena’s answer was to build its own models in Victory Atomistic, which couples the Poisson and Schrödinger equations in one self-consistent solve. Silvaco’s team worked with Ciena to refine the tool. Process data was sparse. Even so, on 5nm devices at room temperature the simulated trends line up with lab measurements. Cryogenic behavior for qubit work is harder: measuring it costs a great deal, so Ciena wants simulation to take over. Convergence at very low temperature and low bias is where the work continues.
Her master’s research at Concordia University (2007) computed eigenstates of multidimensional nanostructures. At Ciena she is responsible for analog circuit verification and for quantum device models. Electrical engineering degree (B.Eng.) from Tabriz University.

Products: Victory Atomistic

Machine Learning for Multi-Scale Plasma Process Integration and Optimization

Associate Professor Dr. Lado Filipovic, TU Wien

A high-aspect-ratio etch has to come out right at two scales at once: across the whole plasma reactor, and inside a single feature. Dr. Filipovic’s group connects the two. Machine-learning surrogates predict the fluxes a feature-scale model needs. They’re trained on experimental data and on equipment simulations from the Hybrid Plasma Equipment Model (HPEM), and they run quickly enough to adjust the model on the fly. The longer aim is a plasma digital twin that could optimize in real time, cutting back on trial-and-error runs and making the process greener.

Associate Professor at TU Wien’s Institute for Microelectronics. The Christian Doppler Laboratory he directs there, which Silvaco supports, models device and sensor processes across scales. His group also works with Fuji Electric and Infineon, and studies 2D materials such as graphene and MoS2 for sensing. IEEE Senior Member; doctorate (2012) and habilitation (2020) from TU Wien.

 

How to Utilize Victory Analytics and Machine Learning to Calibrate TCAD Data

Dr. Stefania Carapezzi, Field Applications Engineer, Silvaco

Calibrating TCAD to measured data usually falls to experts, adjusting parameters by hand until the curves agree. Dr. Carapezzi shows machine learning doing that fit instead. Victory DoE runs your TCAD simulations as a designed experiment and gathers the outputs. Victory Analytics then searches for the parameter set that matches your measurements. Her test case: an AlGaN/GaN HEMT.
She joined Silvaco France in March 2023. Before that she held postdoctoral posts at the Advanced Research Center on Electronic Systems in Bologna and at the University of Montpellier’s LIRMM lab (CNRS). Her TCAD research targeted beyond-CMOS devices and quantum behavior in nanoscale transistors. PhD in physics, University of Bologna, 2014.

Products: Victory Analytics · Victory DoE

Applying Artificial Intelligence in Fab Technology Co-Optimization

Dr. Christian Caillat, TCAD Senior Staff FAE, Silvaco

Every wafer in a split lot costs money and time. A parameter that won’t hit its target can keep a team experimenting for weeks or months. A machine learning model of one process step, simplified but accurate, offers a shorter route, and the approach is already in production use. FTCO builds the model from your fab data and TCAD data together, as a digital twin. Dr. Caillat runs the flow on worked examples, so you can see how it would apply to your own process.
Thirteen years at Micron Technology came before Silvaco. That work spanned advanced memory modeling, the emerging-memory collaboration with imec, and leading the 3D NAND cell team. He has worked for Silvaco from Boise, Idaho, since June 2023. Engineering degree in electronics and PhD in microelectronics from Grenoble.

Products: FTCO

Utilizing Physics-Based AI-Powered Digital Twins to Accelerate Design Optimization and Manufacturing Yield of SiC Power Devices

Dr. David Green, TCAD Applications Engineer, Silvaco

For 18 years he has supported Silvaco’s TCAD customers across EMEA, in pre- and post-sales, on applications from power and display to reliability and optics. From Cambridge, UK, he also manages TCAD R&D projects. His PhD and postdoctoral research covered designing, simulating and testing power devices for integrated circuits.

Power Devices SPICE Modeling with a Detailed SiC DMOS Parameter Extraction Methodology

Dr. Bogdan Tudor, Head of Modeling, Silvaco

Dr. Tudor opens with the options for putting a Si, GaN or SiC power device into SPICE: a compact model, a macromodel or Verilog-A. Then he takes one SiC DMOS all the way through. Its extraction works from I-V and C-V data and deals with the device’s bias-dependent capacitances. After that, the model is tuned against dynamic characteristics, and dynamic temperature effects come last.
Device characterization, compact model development and MOSFET aging reliability are his specialties. Since 2017 he has been at Silvaco, where he heads the Device Characterization Group. His earlier career: 12 years at Synopsys as a senior R&D engineer, then four at ProPlus Design Solutions as principal software architect. MS and PhD from the Polytechnic University of Bucharest.

IC Design Track (EDA and IP)

EDA and IP Updates

Ben Louie, VP and GM of IP Business Unit, Silvaco

What’s new in the Analog and Custom IC tools, feature by feature, and what’s planned next for Silvaco EDA.
Responsible for all of Silvaco’s semiconductor design IP. Over 22 years of memory design lie behind him, from NOR and NAND flash to MRAM. He has worked at Micron and Xilinx and at startups including MagSil, Spin Memory and Zeno Semiconductor. Bachelor’s and master’s in electrical engineering, both from Santa Clara University; 123 US patents issued.

Products: Analog and Custom IC

EDA Solutions for Physical Design of Discrete Power Devices

Stefano Pettazzi, Staff Applications Engineer, Silvaco

In a discrete power device much of the geometry is curved, and curved shapes are where rule checking gets difficult. The layout is drawn in Expert. Verification runs in SmartDRC, which keeps both its speed and its accuracy on curve-heavy designs. A short closing section covers the combined TCAD and EDA flow for power devices, so one supplier handles device physics and physical design.
Close to 25 years in EDA and microelectronics. Since 2012 he has been at Silvaco, supporting customers’ design flows from front end through back end. M.S. in electrical and electronics engineering, University of Pavia.

Products: Expert · SmartDRC/LVS

Accelerating the Verification of High-Frequency Analog Mixed-Signal Components via Jivaro Pro Advanced Parasitic Reduction

Chung-Chun Chen, Director of Analog Design, Silicon Creations

A clocking and SerDes designer whose analog IP at Silicon Creations includes PLLs, CDRs, phase interpolators and equalizers. Before Silicon Creations he worked at TSMC in Hsinchu and Samsung Electro-Mechanics in Atlanta, and he spent 2018 to 2019 at Realtek’s Ubilinx Technology. More than 15 peer-reviewed papers; PhD from National Taiwan University (2009).

Products: Jivaro Pro

Using Viso to Investigate, Analyze and Solve Advanced Parasitics Issues

Carlos Berlitz, Corporate Applications Engineer, Silvaco

Running simulation after simulation to track down a parasitic problem is slow, laborious work on an advanced-node design. Viso works on the extracted RC network itself. It estimates timing, checks crosstalk and compares matching between nets, then highlights the parts of the design that need attention. The demo runs on high-speed circuits, with no long simulation loop in between.
He supports and tests Silvaco’s EDA tools that analyze and reduce RC parasitics, and helps shape their roadmap. He joined in 2023, after circuit design and support roles at other companies. PhD from INSA Lyon, MS from Grenoble Alpes University, BS from UFRGS.

Products: Viso

Standard Cells Characterization Challenges and Improvement

Siti Mariyam, IP Design Enablement, SilTerra

SilTerra’s process technology keeps moving, and each update means another round of library optimization and validation. Siti Mariyam covers where Silvaco tools helped SilTerra’s IP library team through that work, and how characterization time came down as a result.
Her specialty at SilTerra Malaysia is standard cell and IO library development, through to silicon validation. Bachelor’s in electronics system engineering, Universiti Teknologi Malaysia.

Products: Standard Cell

Standard Cell Library IP in Advanced FinFET Nodes for Low Voltage Applications

Fernando Carrion, Design Engineer, Silvaco

FinFETs behave differently as the supply drops toward ultra-low voltage, and standard cells feel it in area, timing, power and variability. After the physics, Fernando Carrion turns to Silvaco’s low-voltage FinFET libraries. They include retention and multi-bit flip-flops, a Power Management Kit (PMK), and high fan-in cells that stack fewer transistors. Multi-threshold variants let you decide where speed matters more than power.
He designs and characterizes standard cells at Silvaco, work he has done for more than four years. An electrical engineering graduate of UFRGS in Brazil, with analog designer certification from the IC Brazil program.

Products: Standard Cell

Advanced Node Library Development with Cello FinFET

Felipe Bortolon, Engineering Manager IP, Silvaco

A new node shouldn’t mean drawing a cell library from scratch. In this demo, Cello FinFET starts from a library you already have and generates GDSII layout automatically from CDL netlists.
Engineering Manager for Cello, the framework Silvaco uses to automate standard cell layout. UFRGS MSc in microelectronics; PUCRS degree in computer engineering.

Products: Cello FinFET

Bandgap References for Low Voltage Operation

Ahmad S. Mazumder, Director of Engineering, Silvaco

0.45 V and 0.92 V: the two bandgap references Silvaco built on TSMC N3P, a 3nm FinFET process. A bandgap reference is meant to hold still while supply, load and process vary. Neither of these drifts more than 1% anywhere from -45°C to 150°C.
He leads development and customer support for Silvaco’s analog and interface IP, and joined its IP division in 2019. Before that came 28 years of high-speed memory, SerDes, ESD and reliability work at C-Cube Microsystems, Broadcom and Intel. MS in VLSI design, City University of New York.

LDO For Low Voltage Operation

Shaikh A Shams, Staff Engineer, Silvaco

No external capacitor, up to 30 mA of load current, and less than 3,400 µm² of area. That’s the LDO Silvaco designed on TSMC N3P 3nm FinFET. It runs from a 1.2 V ±10% input, and you program its output in 50 mV increments from 0.45 V up to 0.9 V. Over every PVT corner from -40°C to 125°C, PSRR holds at more than 40 dB (1 kHz) and more than 29 dB (10 MHz). Across the same corners, a 1 A/ns load step moves the output by less than 18 mV either way.
He develops analog and interface IP in Silvaco’s Analog/Interface IP Division, which he joined in 2020. His 22 years before that, at Dialog Semiconductor, GlobalFoundries and Intel, covered high-speed SerDes, voltage regulators, and AMS design and verification. University of Arizona master’s, electrical and computer engineering.

Introduction to CAN-XL

Mauricio Brochi, Director of Automotive IP, Silvaco

Three generations of the Controller Area Network in one talk. The 1986 original let the highest-priority frame take the bus without corrupting the others, and cut off a faulty node so the rest could carry on. Larger ECU data packages exposed its throughput ceiling, and CAN FD answered in 2011 with 8 Mbps and 64-byte payloads. CAN XL goes to 20 Mbps, with payloads of 2,048 bytes. It also links to Ethernet standards including 10BASE-T1, which matters as vehicles move to software-defined architectures.
Automotive and industrial SoC systems and IP have been his field for more than three decades. At Motorola, and later NXP, he worked on CAN controllers, automotive timers and low-power controllers as well as microcontroller cores. Electronic engineering degree, University of Campinas, Brazil.

Products: Automotive IP

Themes at SURGE EMEA 2025

Three talks on SiC and discrete power: digital twins, DMOS SPICE extraction and curved-layout DRC

Quantum transport at Ciena, machine learning for plasma etch at TU Wien, and the Victory update

SilTerra’s characterization work, low-voltage FinFET libraries and Cello FinFET automation

Digital twins of fab process steps, and TCAD calibration using Victory DoE and Victory Analytics

Jivaro Pro at Silicon Creations, parasitic analysis in Viso, and the portfolio update

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