Concluded event

SURGE Virtual Event China 2025

China · Friday, January 17, 2025 · 13:00–17:00 Beijing time · Virtual event

At a glance

January 17, 2025

Date

China

Region

Virtual

Format

19

Sessions in 3 tracks

About this event

SURGE China 2025 ran online on the afternoon of Friday, January 17. Four hours, 19 talks.

SURGE is the conference Silvaco holds for the people who use its tools, so they can keep learning from one another. This edition brought a quantum-transport study from Ciena, machine learning for plasma etching from TU Wien and cell-library characterization from SilTerra Malaysia. Silicon Creations and 粤芯半导体 presented too, alongside Silvaco’s own updates on TCAD, EDA and IP.

Tracks

Agenda

Recordings for all 20 SURGE North America 2025 talks sit on Silvaco’s support site. To open
one, sign in there or complete a short form with a work, university or government email.

主会场

公司最新进展

Babak Taheri 博士,Silvaco,CEO及董事会成员

人工智能如何将EDA推向新高度

Wally Rhines,Cornami 总裁及CEO、Silvaco董事会成员

半导体工艺和器件分会场

TCAD最新进展

Eric Guichard 博士,Silvaco,公司高级副总裁及TCAD事业部总经理

Where the Victory TCAD simulation products stand today, and why TCAD carries so much weight in developing a new device. Then, the direction TCAD development takes from here.

Products: TCAD

通过量子传输仿真研究纳米线晶体管的低温特性

Sanam Moslemi-Tabrizi,Ciena,模拟工程师

Quantum effects take over at the nanoscale, and classical simulators can’t see them. So Ciena’s analog team began building its own device models rather than relying only on supplied ones. Victory Atomistic, which solves the Poisson-Schrödinger equations self-consistently, met Ciena’s first requirements, and the two companies then worked together to extend it. For Ciena’s 5nm devices at room temperature, the simulated trends track lab data. Next comes qubit research, where simulation is meant to replace expensive cryogenic measurements. Convergence at the lowest temperatures and bias levels is still being improved.

Products: Victory Atomistic

用于多尺度等离子体工艺集成和优化的机器学习

Lado Filipovic 博士,TU Wien,副教授

In plasma etching, the hard part is keeping reactor-scale chamber conditions and feature-scale profiles in step. Dr. Filipovic covers equipment-informed feature-scale models and machine-learning surrogates. The surrogates learn from experimental data and from equipment simulations, the Hybrid Plasma Equipment Model (HPEM) among them. Their flux predictions come fast enough to point toward real-time optimization of the high-aspect-ratio structures that CMOS and emerging devices depend on. The payoff is fewer trial-and-error runs in the fab.

使用TCAD软件应对研发过程中的工艺和器件挑战

高沛雄 博士,粤芯半导体,TCAD仿真经理

在Fab Technology Co-Optimization中应用人工智能技术

Christian Caillat 博士,Silvaco,TCAD应用工程师

Fab optimization usually means Design of Experiments on real wafers, and each experimental round can run for weeks or months. Machine learning offers another route, and it’s already in production use: model one fabrication step in software, accurately enough to trust. FTCO builds that model from your fab and TCAD data, as a digital twin. Dr. Caillat walks through the FTCO flow on worked examples.

Products: FTCO

功率器件SPICE建模——SiC DMOS参数提取方法研究

Bogdan Tudor 博士,Silvaco,建模负责人

Power device SPICE models for Si, GaN and SiC, built with compact models, Verilog-A or macromodels. Most of the talk follows a single SiC DMOS through extraction. It fits the I-V and C-V data and handles the bias-dependent capacitances. Then it tunes the model against dynamic behavior and captures dynamic temperature effects.

功率器件物理设计的EDA解决方案

Stefano Pettazzi,Silvaco,应用工程师

Physical design and verification decide whether a discrete power device performs reliably and can be manufactured. Power layouts are full of curved shapes, and DRC engines commonly struggle with them. The session shows Expert building those layouts and SmartDRC verifying curved geometry quickly without trading away accuracy. It closes with a short look at running TCAD and EDA for power devices from one vendor.

IC设计分会场

EDA和IP最新进展

Ben Louie,Silvaco,公司副总裁及IP事业部总经理

Silvaco’s analog and custom design tools: their new features and functionality, and where the EDA line goes next.

Jivaro Pro高级寄生参数缩减

Chung-Chun Chen,Silicon Creations,模拟设计总监

Products: Jivaro Pro

使用Viso探索、分析和解决高级寄生问题

Carlos Berlitz,Silvaco,应用工程师

Parasitics can do real damage to an advanced-node design, and chasing them through simulation is slow work. Viso analyzes RC parasitic networks directly, estimating timing, crosstalk and matching between nets, and it highlights where in the design the trouble sits. Carlos Berlitz demonstrates it on high-speed circuits, without repeated long simulation runs.

Products: Viso

标准单元库特征化的挑战与改进

Siti Mariyam,SilTerra Malaysia,高级IP工程师

A working foundry changes its processes often, and every change means re-optimizing and revalidating its IP libraries. SilTerra shows where Silvaco tools sit in its library development flow, and how they shorten characterization.

Products: Standard Cell

先进FinFET工艺中的低电压标准单元库IP设计

Fernando Carrion,Silvaco,研发工程师

Low supply voltage changes how standard cells behave at advanced FinFET nodes: area, timing, power and variability all shift. Fernando Carrion starts with those effects, then moves to Silvaco’s low-voltage libraries for FinFET nodes. They include multi-bit and retention flip-flops, high fan-in cells built on shorter transistor stacks and a Power Management Kit (PMK). Multi-threshold options let you set the performance-power balance your design needs.

Products: Standard Cell

使用Cello FinFET进行先进工艺节点单元库开发

Felipe Bortolon,Silvaco,工程经理

Cello FinFET cuts the work of building cell libraries for advanced nodes. Felipe Bortolon shows two uses: carrying an existing library onto a new node, and generating GDSII from CDL files automatically.

Products: Cello FinFET

低电压设计的Bandgap基准

Ahmad S. Mazumder,Silvaco,工程总监

A bandgap reference holds its voltage nearly flat as supply, load, time, temperature and process move. Silvaco designed two in TSMC N3P 3nm FinFET: a 0.45 V low-voltage reference and a 0.92 V higher-voltage one. Each stays within 1% from −45°C to 150°C.

低电压设计的LDO

Shaikh A Shams,Silvaco,应用工程师

This capless LDO, in TSMC N3P 3nm FinFET, supplies up to 30 mA. From a 1.2 V ±10% input, you can set its output anywhere between 0.45 V and 0.9 V, in 50 mV steps. Across PVT corners from −40°C to 125°C, it holds PSRR above 40 dB at 1 kHz and above 29 dB at 10 MHz. On a 1 A/ns load step, undershoot and overshoot stay under 18 mV. All of it fits in less than 3,400 µm².

CAN-XL汽车总线IP介绍

Mauricio Brochi,Silvaco,汽车IP总监

How the CAN bus grew into CAN XL. The first CAN protocol, from 1986, arbitrated without destroying frames, so high-priority traffic won the bus and faulty nodes dropped off. CAN FD arrived in 2011, with up to 8 Mbps and 64-byte payloads. CAN XL raises that to 20 Mbps and 2,048 bytes. It also connects to Ethernet standards such as 10BASE-T1, for in-vehicle networks that now include software-defined vehicles.

 

Products: Automotive IP

Themes at SURGE North America 2025

From SiC digital twins to DRC on curved discrete-device layouts

The Victory TCAD update, and TCAD in 粤芯半导体’s process and device R&D

Library characterization at SilTerra, low-voltage FinFET cells and Cello FinFET

Applying AI to Fab Technology Co-Optimization

Parasitic reduction with Jivaro Pro and parasitic analysis with Viso

Related

SURGE

The user conference, its 2026 program and the full archive

SURGE 2026

USA, EMEA, Japan and China, February 24 to March 19, 2026

SURGE 2025, China

January 15, 2025 · Virtual event

SURGE 2025, EMEA

January 21, 2025 · Virtual event

SURGE 2025, Japan

January 23, 2025 · Virtual event

Events

SISPAD, IEDM and the other shows Silvaco attends

Webinars

Recent topics include Utmost IV model extraction and plasma chamber simulation