October 2026

Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R Example 5 demonstrates the practical use of a biquad circuit configuration (see biquad.png pngview) to realize a notch filter. The four-opamp biquad circuit

Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R The amplifier design shown in current_mirror_schematic.png uses the bipolar differential pair as the main component in the circuit. Looking at R1=R2 and Q1

Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R Example 7 is a 4th order lowpass filter design using the Generalized Impedance Converter (GIC) method (see GIC.png pngview). The GIC is practical

Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R Example 8 demonstrates a 5-Stage VCO design using a level=54 BSim4 SmartSpice model (see schematic.png). The circuit can be used to generate clock

Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R The schematic of the JFET sampling gate (see schematic.png) shows the J1 JFET device used as a switch to sample the instantaneous amplitude

Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R The three phase schematic example ( schematic.png) shows a source of three identical voltage sources that are phase shifted by 120 degrees. The

Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R This example illustrates use of inherited nets on logic symbols that have explicit pins for power, substrate, and ground (see schematic.png ). In

Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R The illustrates using net property definitions on the symbol instances (see Example12.png). For X1, VCC! is passed in for POWER and GND! is

Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R This example is a ring oscillator hierarchical schematic which illustrates the use of the netInherit symbol (see Example13.png). This symbol is from the

Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R This example is a testbench schematic for testing MOS models and devices (see Example14.png). In this example, a LEVEL=1 NMOS device is simulated,