Casey Molver

When you run a long simulation time analysis the evaluated time points are normally all held in memory until the end time is reached. All the data is then written

Guardian LVS from Silvaco is an efficient, reliable, and diverse package that brings the benefit of high-speed verification to PC-based test environments. Guardian netlist extractor, included with the Guardian suite,

Silvaco’s Guardian LVS tool compares two circuits that are defined by their netlists. The comparison is based strictly on the topological structure of these circuits. Topologically equivalent netlists are considered

I generated some layers in Expert by DRC script run, and after that, derived layers can not be cleaned by "Tools\Derived Layers\Clean Derived Layers\ Whole Project", otherwise, derived layers generated

Recent years has seen rapid acceleration in the research and development of organic thin film transistors (OTFTs) as key components for active matrix displays, radio frequency identification tags, and many

Exact2 from Silvaco is a sophisticated, physically-based simulation tool for calculating semiconductor interconnect capacitance values. Its purpose is to build a capacitance coefficient database that is usable by any layout

This article addresses the creation of semiconductor laser double heterostructures, and the subsequent simulation of laser output with DevEdit from Silvaco. A laser consists of a gain medium sandwiched between

Computer simulation is used extensively to verify physical phenomena in semiconductor devices. Meshing plays an essential role in obtaining good simulation results. If care is not properly taken, serious errors

ATHENA’s Optolith module is designed to simulate the 3 basic lithography technologies; contact printing, proximity and projection lithography. The imaging calculations within Optolith are flexible enough to handle all three

This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is also formulated and shown

This article focusses on the use of Silvaco International’s schematic capture and editing tool Scholar combined with Verilog A. Verilog A is a standard language used for behavioral level modeling.

This simulation standard will discuss Silvaco International’s post processing application SmartView and will highlight features that identifying it as an important tool to the design engineer. In particular, the integration