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Mixel IP Silvaco’s Mixel product line of silicon-proven mixed-signal interface IP:MIPI D-PHY, C-PHY and M-PHY, C-PHY/D-PHY combo and LVDS/D-PHY combos, LVDS, and ASA Motion Link. See available IP Talk to

Design IP: Production-Ready Offerings for Production-Ready SoCs Production-Ready Offerings (PRO IP) for SoC designs, characterized for specific foundry processes and available to license now: Mixel mixed-signal interface IP, standard cell

PEX Certify: qualify and compare parasitic extraction flows PEX Certify shows you, net by net, whether your parasitic extraction flow still agrees with itself after a PDK or extractor change,

VarMan XMA: full-chip memory yield analysis Estimate yield for the whole memory, not a slice of it. VarMan XMA rebuilds the full array and runs Monte Carlo across it, so

VarMan: statistical variation and yield analysis for analog, library and memory Know how your circuit behaves across process variation before silicon tells you, with Monte Carlo-accurate results up to 30X

Viso: Schematic Viewer for SPICE Netlist Files Load a parasitic netlist and see which nets the layout is hurting, and why, before you queue a long post-layout simulation. Talk to

Jivaro Pro: parasitic reduction for post-layout SPICE simulation Your design is ready… but your simulation is still running… Accelerate post-layout SPICE simulation, run larger designs and get more engineering work

Hipex: full-chip rule-based RC parasitic extraction Hipex runs parasitic extraction on the full chip or only the nets you pick, then writes the resistance and capacitance your layout adds back

SmartDRC/LVS: physical verification for analog, digital and mixed-signal ICs Check a layout against your foundry’s rules and its own schematic, then debug the results in your layout editor. Talk to

Gateway: hierarchical schematic editor for analog and mixed-signal design Capture an analog, digital, mixed-signal or RF IC design once. Gateway netlists that one schematic for simulation, layout and LVS, so

Expert: hierarchical analog layout editor for mixed-signal and RF ICs Analog layout, checked against design rules while you draw it. The editor opens designs larger than 10 GB in minutes.

Circuit Rubberband: real-time circuit tuning in SmartSpice Change a model or device parameter and watch the waveforms answer, so you settle the value in one sitting, not one rerun at