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1 week ago

019_5th_order_lp_filter : 5th order LP Filter variations

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 4.6.5.R The circuit input deck is a 5th-order Lowpass filter containing pole zero analysis (.PZ). Rubberband r*[res], c*[cap] and l*ind] parameters to see

1 week ago

001_mos_op : MOS OP point

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R In this input deck a simple MOS level=3 device is optimized against a DATA set for a DC family of curves and

1 week ago

002_dc_op : Modulated sources as single element in circuit.

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R This input deck shows you how to produce a single element Frequency Modulated Source . Input Files mod1.in Parametric analysis ***** Circuit

1 week ago

003_ac_op : Verilog-A

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R The input deck Input Files mod1.in Parametric analysis ***** Circuit description vcc vss 0 DC vccDC vin inp 0 PULSE(0 3 0

1 week ago

004_tran_op : IBIS Buffer

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R Example 4 illustrates The input deck file ….. Input Files mod1.in Parametric analysis ***** Circuit description vcc vss 0 DC vccDC vin

1 week ago

005_buffer_delay : Buffer delay/risetime optimized for Vdd

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R The input deck contains a buffer circuit to be optimized for geometry (W/L) to get the best rise, fall and delay times

1 week ago

001_example_1 : Save and Recover to restart simulation

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R SmartSpice has ability to save a long simulation to files at specified checkpoints for further recovery and continuation in the case of

1 week ago

001_biaschk : Biascheck functionality

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R A 13 stage ring Oscillator built with fictional BSIM4 models is used to show how you can setup the .BIASCHK functionality to

1 week ago

002_biaschk3 : Bias checking of device

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R The .BIASCHK3 statement is intended to track and report the maximum duration time (dt) when the voltage difference between the specified device

1 week ago

003_dot_dout : Dout (Expected State of Digital Output Signal)

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R The .dout statement compares simulation results (node voltage) with the expected digital state during the transient analysis and generates an output report.