• Guardian

Guardian DRC/LVS/Net Physical Verification

Guardian performs physical verification of analog, digital and mixed-signal ICs including design rule checks (DRC), layout netlist extraction and layout vs schematic (LVS) comparisons. It is architected to deliver high performance and capacity using multi-threaded batch processing of large hierarchical designs, accurate processing of complex shapes and exceptional user productivity with fast interactive verification and intuitive debug.


Increasingly complex designs together with shrinking process geometries are driving the need for a highly productive physical verification environment. This includes the ability to rapidly setup rule and technology files, an efficient data flow from design entry to verification, and the verification tools’ capacity and performance to process huge hierarchical designs quickly. Users need easy design navigation within the tools, intuitive visualization, rapid debug and resolution of identified errors. Accurate calculation of geometry dependent SPICE parameters is crucial, as is the ability to correctly process complex shapes and all-angle objects.

Guardian has unique capabilities to meet these growing requirements. Exceptional performance is delivered through the use of multi-threaded processing, optimized layer operations, efficient memory management and advanced algorithms. Guardian features a tight integration with the Expert layout editor. This integration enables users to visualize and pinpoint design issues and design rule violations and quickly act to resolve them. Guardian extracts the netlist from layout for final simulation and provides the user the ability to cross-compare the schematic, logical netlist, layout and physical netlist.

Guardian’s performance, accuracy and user productivity meet the challenging requirements for the physical verification of today’s complex analog and mixed-signal circuits.


  • High performance batch processing of large hierarchical designs
  • Easy navigation and visualization through graphical and text DRC error reports – intuitive for new users and experts
  • Hierarchical DRC error reporting maximizes efficiency of layout debugging
  • Connectivity-based DRC operations including antenna rule checking
  • Supports 90, 45-degree and all-angle objects with no compromise in accuracy
  • Multithreading DRC offers dramatic increase in performance and capacity
  • Hierarchical LVS verifies huge circuits and reduces processing time, memory usage and LVS discrepancy counts
  • Intuitive, hierarchical LVS reporting and debugging
  • Cross-probing of discrepancies between layout and schematic views with Expert and Gateway
  • Perform Layout Vs Layout verification (LVL)
  • Blackbox options for subcircuits provides for incremental LVS comparison in hierarchical mode and easy inclusion of IP blocks into verified design at top level
  • Precise identification of generic devices (transistors, diodes, resistors, capacitors, etc.), user-defined devices and/or black-box sub circuits during LVS trace
Netlist Extraction
  • Efficient, full-chip layout netlist extraction for semiconductor processes with unmatched performance
  • Hierarchical engine preserves the design hierarchy in netlist for easy analysis
  • Detects ERC violations (shorts, opens, dangles and improperly connected devices) with convenient filtering options
  • Supports stress effects and well proximity parameter extraction
  • Accurate calculation of geometry dependent SPICE parameter important for analog design with default or user-defined equations
  • Handles any arbitrary shaped polygon geometry used in device formation and all standard devices such as MOSFET, BJT, MESFET, JFET, capacitors, resistors and diodes


  • Highly productive physical verification environment
  • Quick resolution of DRC errors using Expert
  • Rapid verification of extremely large designs


  • Analog, Digital, Mixed-signal and RF

Technical Specifications

  • Integration with Silvaco’s Expert Layout and Gateway Schematic Editors
  • Input files to Guardian: DRC/LVS/LPE Rule files, GDSII, OASIS, SPICE netlist (Flat or Hierarchical)
  • Output netlist format: Hierarchical DRC/LVS/NET Error report, Extracted layout SPICE netlist
  • Broad support of semiconductor process technologies through PDKs

Analog Custom Design Resources

Analog Simulation
Analog Custom Design & Analysis
Model Generation
Guardian DRC
Utmost IVGuardian LVS
Parasitic Extraction
Gateway – Schematic CaptureJivaro– Parasitic Reduction for Fast, Accurate Simulation
Expert – Layout EditorViso – Parasitic Analyzer and Debugger
Guardian – DRC/LVS/Net Physical VerificationBelledonne – Layout Parastic Extraction Comparison
SmartSpice – Circuit SimulatorVarMan – Statistical Variation and Yield Analyzer
SmartView – Waveform AnalyzerVarMan XMA Option – Full-chip RAM Yield Analyzer
SmartSpice RadHard – Radiation Effects Circuit SimulatorVarMan for Libraries – Library Statistical Functional Verification
SmartSpice Pro– FastSPICE SimulatorUtmost IV– Device Characterization and SPICE Modeling
Hipex – Full-Chip Parasitic ExtractionUtmost IV Quick-Start– Model extraction and Optimization Templates
InVar IR – Drop and Thermal AnalysisTechModeler – Verilog-A Blackbox Device Modeling

Learn How Silvaco’s SmartSpice is Getting Faster

Good News – The Silvaco Analog Custom Design Flow

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Customer Interview: Why I Rely on SmartSpice

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Kunihisa Ishii
 More customers will be able to use our six-inch silicon foundry with our new 0.35 µm CMOS PDK for Silvaco custom design tools. With our partnership with Silvaco, who have a lot of experience in analog custom design solutions, we will reduce total development costs for our customers and extend our flexible foundry services.