Learn How Silvaco Flow Helps Designing and Simulating Pixel Arrays in Flat Panel Displays and Detectors
Designers of flat panel displays and detectors often rely on a variety of point tools from different EDA vendors that make the design flow discontinuous and difficult to integrate. These challenges, together with specific advanced display technology requirements, are addressed by the seamless and unique Silvaco TCAD-EDA flow.
This webinar highlights how leading display and detector companies exploit the capabilities of Silvaco tools for schematic and layout editing, very accurate field solver-based parasitic extraction required by modern TFT technology, back-annotation of parasitic RC elements into the netlist, and fast and accurate SPICE simulations of large arrays of pixels.
What You Will Learn
- Challenges of FPD and detector design
- Designing and simulating pixel arrays by adopting Silvaco’s seamless TCAD to EDA design flow
- Field solver-based parasitics extraction
Presenter
Stefano Pettazzi, Senior Applications Engineer, Silvaco, Inc.
Stefano Pettazzi received his M.S. degree in Electrical and Electronics Engineering from University of Pavia, Italy. He has more than 20 years of experience in EDA and microelectronics companies. Since 2012, he has been working at Silvaco as Senior Applications Engineer supporting EDA software for both back-end and front-end design flows.
WHO SHOULD ATTEND:
Display designers, analog circuit designers, CAD and SoC design engineers, product managers, and engineering management in the circuit simulation field.
When: June 30, 2022
Where: Online
Time: 10:00am-10:30am-(PDT)
Language: English