Silvaco’s IP offers production proven AMBA IP cores and subsystems.
| Protocol | Title | Features |
|---|---|---|
| AXI | AXI External Memory Controller | AXI-4, AHB, 8/16/32 and 64-bit external modes up to 4 external devices |
| AXI QSPI Controller | AXI-4, XIP support, DMA, Quad/Dual mode, Full/half duplex operation | |
| AXI / SPI Slave Bridge | Read / Write Access to AXI subsystem registers & memories | |
| AXI 5-Master SRAM Controller | Low Latency with zero or one cycle access to 64-bit SRAM | |
| AHB | AHB Octal / Quad SPI Controller | AHB, 4/8/32-bit operation, Full/half duplex, Dual/quad modes |
| AHB Arbiter | AHB 2.0, Up to 4 masters using round-robin mechanism | |
| AHB DES / Triple DES | AHB 2.0, AHB DES/TDES mode, DMA master, Elliptical curve | |
| AHB AES with DMA | ECB/CBC/OFB, 128/192/256-bit key lengths | |
| AHB Single/Quad DMA Controller | AHB 2.0, 1/4-channel, Single/programmable burst, Linked-list support | |
| SPI to AHB-Lite Bridge | Read/write access to AHB-Lite sub-system | |
| AHB-Lite Slave to SPI Master | Supports 4 slaves and all SPI modes | |
| AHB External Bus Interface | Supports 8-bit, 16-bit, 32-bit access | |
| AHB TFT LCD Controller | Supports 24-bit, 16-bit, 8-bit color LCD panels | |
| AHB SRAM Controller | Zero wait state 8-bit, 16-bit, 32-bit access to SRAM | |
| AHB Parallel Flash Controller | AHB bus to Parallel SuperFlash device supports 8/16/32-bit external modes, 8/16/32-bit AHB access | |
| APB | APB GPIO | APB 2.0, Scalable up to 32 I/Os, Interrupt support, Software configurable |
| APB Real Time Clock | APB 2.0, Clock/calendar BCD format with interrupt support | |
| APB Interrupt Controller | APB 2.0, Up to 32 independent channels | |
| APB Pulse Width Modulator | APB 2.0, Prescalar/non-prescalar mode, 4-bit prescalar | |
| APB Timer | APB 2.0, 16-bit counter/timer, 10-bit prescaler, RTOS time base | |
| APB UART | APB 2.0, programmable baud rates, DMA interface, interrupt support | |
| APB Watchdog Timer | APB 2.0, 16-bit R/W bus, 10-bit address bus, Interrupt support, DFT signals/wp-content/uploads/product/ip/pdf/70124_IPC-Timer-APB_brief.pdf | |
| AMBA Bus Fabrics / Bridges | AHB Multi Fabric | AHB 4, Support up to 4 masters and 7 slaves |
| AXI Multi Fabric | AXI 4, Support up to 4 masters and 8 slaves | |
| AXI / AHB Bridge | AXI 4, AHB Lite, 2-clock domains with FIFO support | |
| AHB / AXI Bridge | AXI 4, AHB Lite, 2-clock domains with FIFO support | |
| AHB / APB Bridge | APB 3.0, 2.0, Low latency, Low gate count | |
| AHB Bus Channel + Decoder | APB 3.0, 2.0, Support up to 16 slaves | |
| APB Bus Channel + Decoder | AXI 4, AHB Lite, 2-clock domains with FIFO support | |
| AHB-Lite to AHB-Lite Asynchronous Bridge |
Bridge asynchronous AHB-Lite domains for any clock freq. ratio | |
| APB to AHB-Lite Asynchronous Bridge | Bridge asynchronous APB and AHB-Lite domains for any clock freq. ratio | |
| AXI / APB Bridge | AXI 4, APB 3.0, 2.0 | |
| AMBA Subsystems | I3C Sensor APB | MIPI I3C, APB 3.0, I2C backward compatible, SDR/DDR mode, IBI (In Band Interrupt) |
| AHB Low-power | AHB 2.0, APB 3.0, Power management, Boot code, Basic kernel support | |
| AHB Performance ARM-M0 / ARM-M3 | AHB 2.0, APB 3.0, PMU, RTOS/Kernel support, DMA | |
| AHB Secure M3 | AHB 2.0, APB 3.0, Secure AHB Fabric, SRAM and ROM Parameterized MPUs, PMU, RTOS/Kernel support, DMA | |
| AXI Performance | AXI 4.0, AHB 2.0, APB 3.0 Multi-layer Fabric, QSPI RTOS/Linux support |
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Rick Lazansky
Over the past two years, Silicon Catalyst has been working with key industry players to develop a complete ecosystem that economically and effectively supports the new wave of semiconductor startups that we are seeing today. Our Portfolio Companies have consistently been requesting IP as the critical element that we had not been able to deliver. Silvaco’s offering fulfills a real hole that has been impeding the success of these startups. We are glad to deliver this capability as we continue to build the semiconductor start up ecosystem.
Silicon Catalyst
CEO
Srinath Anantharaman
The integrated solution enables design teams to collaborate efficiently in a secure design environment when developing their IPs or SoCs either locally or across multiple design sites. It enables design teams to successfully tapeout their designs by mitigating the risk by sharing and using the correct version of the design data and IPs.
ClioSoft
CEO
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