• AMBA IP Cores and Subsystems

Silvaco’s IP offers production proven AMBA IP cores and subsystems.

AXIAXI External Memory ControllerAXI-4, AHB, 8/16/32 and 64-bit external modes up to 4 external devices
AXI QSPI ControllerAXI-4, XIP support, DMA, Quad/Dual mode, Full/half duplex operation
AXI / SPI Target BridgeRead / Write Access to AXI subsystem registers & memories
AXI 5-Controller SRAM ArbiterLow Latency with zero or one cycle access to 64-bit SRAM
AHBAHB Octal / Quad SPI ControllerAHB, 4/8/32-bit operation, Full/half duplex, Dual/Quad/Octal modes, XIP and PSRAM support
AHB ArbiterAHB 2.0, Up to 4 controllers using round-robin mechanism
AHB DES / Triple DESAHB 2.0, AHB DES/TDES mode, DMA controller, Elliptical curve
AHB AES with DMAECB/CBC/OFB, 128/192/256-bit key lengths
AHB Single/Quad DMA ControllerAHB 2.0, 1/4-channel, Single/programmable burst, Linked-list support
SPI to AHB-Lite BridgeRead/write access to AHB-Lite sub-system
AHB-Lite Target to SPI ControllerSupports 4 targets and all SPI modes
AHB External Bus InterfaceSupports 8-bit, 16-bit, 32-bit access
AHB TFT LCD ControllerSupports 24-bit, 16-bit, 8-bit color LCD panels
AHB SRAM ControllerZero wait state 8-bit, 16-bit, 32-bit access to SRAM
AHB Parallel Flash ControllerAHB bus to Parallel SuperFlash device supports 8/16/32-bit external modes, 8/16/32-bit AHB access
APBAPB GPIOAPB 2.0, Scalable up to 32 I/Os, Interrupt support, Software configurable
APB Real Time ClockAPB 2.0, Clock/calendar BCD format with interrupt support
APB Interrupt ControllerAPB 2.0, Up to 32 independent channels
APB Pulse Width ModulatorAPB 2.0, Prescalar/non-prescalar mode, 4-bit prescalar
APB TimerAPB 2.0, 16-bit counter/timer, 10-bit prescaler, RTOS time base
APB UARTAPB 2.0, programmable baud rates, DMA interface, interrupt support
APB Watchdog TimerAPB 2.0, 16-bit R/W bus, 10-bit address bus, Interrupt support, DFT signals
AMBA Bus Fabrics / BridgesAHB Multi FabricAHB 4, Support up to 4 controllers and 7 targets
AXI Multi FabricAXI 4, Support up to 4 controllers and 8 targets
AXI / AHB BridgeAXI 4, AHB Lite, 2-clock domains with FIFO support
AHB / AXI BridgeAXI 4, AHB Lite, 2-clock domains with FIFO support
AHB / APB BridgeAPB 3.0, 2.0, Low latency, Low gate count
AHB Bus Channel + DecoderAPB 3.0, 2.0, Support up to 16 targets
APB Bus Channel + DecoderAXI 4, AHB Lite, 2-clock domains with FIFO support
AHB-Lite to AHB-Lite
Asynchronous Bridge
Bridge asynchronous AHB-Lite domains for any clock freq. ratio
APB to AHB-Lite Asynchronous BridgeBridge asynchronous APB and AHB-Lite domains for any clock freq. ratio
AXI / APB BridgeAXI 4, APB 3.0, 2.0
AMBA Subsystems
AHB Low-powerAHB 2.0, APB 3.0, Power management, Boot code, Basic kernel support
AHB Performance ARM-M0 / ARM-M3AHB 2.0, APB 3.0, PMU, RTOS/Kernel support, DMA
AHB Secure M3AHB 2.0, APB 3.0,  Secure AHB Fabric, SRAM and ROM Parameterized MPUs, PMU, RTOS/Kernel support, DMA
AXI PerformanceAXI 4.0, AHB 2.0, APB 3.0 Multi-layer Fabric, QSPI RTOS/Linux support

Contact Silvaco if you need additional info on a specific IP or you do not see the IP product you require.





Rick Lazansky
 Over the past two years, Silicon Catalyst has been working with key industry players to develop a complete ecosystem that economically and effectively supports the new wave of semiconductor startups that we are seeing today. Our Portfolio Companies have consistently been requesting IP as the critical element that we had not been able to deliver. Silvaco’s offering fulfills a real hole that has been impeding the success of these startups. We are glad to deliver this capability as we continue to build the semiconductor start up ecosystem. 
Srinath Anantharaman
 The integrated solution enables design teams to collaborate efficiently in a secure design environment when developing their IPs or SoCs either locally or across multiple design sites. It enables design teams to successfully tapeout their designs by mitigating the risk by sharing and using the correct version of the design data and IPs.