• Jivaro Pro

Jivaro Pro – Parasitic Reduction

Turbocharge Your SPICE Simulations for Lightning-Fast Results

Leading IDM and fabless companies worldwide have adopted Jivaro Pro to address the increasing challenges of managing the time and resource challenges of post-layout simulations. Jivaro Pro applies patented mathematical approaches of parasitic reduction to reduce circuit complexity while maintaining accuracy.

Jivaro Pro SPICE Acceleration

For technology nodes from 65nm down to 3nm, Jivaro Pro is independent of the extraction and simulation tools and plugs directly into any design flow. In contrast to rules-based and embedded reduction methods, Jivaro Pro allows designers unparalleled flexibility in managing the tradeoff between accuracy and reduction. For ease of use, Jivaro Pro provides an automatic mode capability that adapts to your design. There are also over 30 adjustable parameters to enable broad control over speed and accuracy of results.

With Jivaro Pro, the designer is in complete control, allowing complete adaptability to the flow and the type of designs or challenges, providing a single solution for all use cases.

Targeted Reduction – Block or Net


  • Up to 15X post-layout SPICE simulation speedup
  • Easy plug-n-play into existing flows
  • Enables running the largest or previously impossible simulations
  • Include power nets and metal fills in simulations for greater accuracy
  • Customizable parasitic reduction strategies to meet your objectives
  • Increase coverage via more simulations
  • Minimize compute resources (i.e., CPU and Memory configuration)


  • Accepts R, RC, RCC, RLC, RLCK, controlled sources
  • Supports DSPF, SPEF, SPICE3, HSPICE®, SPECTRE®, Calibre® View, OA databases
  • Reduces temperature-dependent parasitic networks and multi-corner extracted netlists
  • Reduction can be applied selectively on nets, sub-circuits or paths within the hierarchy
  • Intuitive GUI for configuration and analysis
  • Jivaro Pro is compatible with all major EDA tools

“… a full simulation on one of our blocks would run 20+ days. After using Jivaro Pro this runtime was reduced to 6 days …”

“eTopus provides ultra-high speed mixed-signal semiconductor IP for high-performance computing and data center applications. In our current FinFET design flow we were experiencing longer than expected post layout SPICE simulation runtimes, especially on the larger blocks where full simulations can run for several weeks.

We approached Silvaco with this issue and were introduced to their Jivaro Pro parasitic netlist reduction tool. We were able to easily ramp up and integrate Jivaro Pro as part of our existing design flow.

After running Jivaro Pro, we were able to significantly reduce our post-layout simulation runtime while maintaining accuracy. As an example, a full simulation on one of our blocks would run 20+ days. After using Jivaro Pro this runtime was reduced to 6 days while maintaining the designer’s accuracy requirements. This 2 – 3X speedup saved us weeks of simulation time and substantially increased our engineering productivity which helps ensure our time to market goals.”

Harry Chan, Founder and CEO