• Simulation Standard Technical Journal

Simulation Standard

Technical Journal

A Journal for Process and Device Engineers

Simulation Framework for Device-packaging Co-design for Power Electronics

The past several years has seen a fast deployment of wide-bandgap power devices in fast chargers, electric vehicles, data centers and renewable energy processing. The performance of power devices is fast progressing towards their intrinsic material limit. As these devices can handle higher voltage and larger current density, packaging and thermal management will become the key limiting factor for exploiting their benefits in power electronic converters and systems.

Understanding of Geometrical Boundary Conditions in Victory Process

It is common to run the process simulation for the part of a larger structure just to reduce the computation time. To account for the influence of parts of the structure outside the simulation domain, Victory Process makes assumptions about overall structure geometry.

Automatic Grid Refinement for Thin Material Layer Etching in Process TCAD Simulations

The utilization of thin material layers is common in modern semiconductor device fabrication. Subsequent etching steps require an accurate modeling of these thin layers. Although level-set based process TCAD simulations are capable of representing flat thin material layers with sub-grid accuracy, topographical changes during etching processes expose the low underlying grid resolution, which leads to detrimental artifacts.

How to Search, View and Use Default Parameters from the Silvaco Material DataBase SMDB with DeckBuild

Silver, DeckBuild’s material database viewer, can be used to examine the default parameters in the Silvaco Material DataBase (SMDB) and to generate MATERIAL commands for Victory Process and Victory Device. Silver can be started by clicking the launch button in DeckBuild.

3D TCAD Simulation of Gallium Nitride Tri-gate Junction HEMT

The GaN high electron mobility transistor (HEMT) has been commercialized as a power device with performance superior to Si devices in the voltage classes from 15 V to 900 V [1]. Most of commercial enhancement-mode (E-mode) HEMTs comprise a planar p-GaN gate. Recently, 3-D gate stacks, such as FinFET and tri-gate structures, have been introduced to lateral GaN HEMTs. They can realize superior gate controllability and E-mode operation with a higher current on/off ratio and lower gated channel resistance [2].

Writing an Impurity Activation Model with the Open Model Library

Accuracy of Impurity Activation is essential in correctly modeling and simulating Silicon Carbide devices. For high concentrations of dopants, it is well known that less than 100% of dopants will be electrically active. To address this effect, Silvaco Victory Process models dopant activation in Silicon Carbide in 3 ways.