Latest Software Baseline Release Notes
The release notes linked below contain the latest changes and new features of every version of our products in the latest software baseline.
Analog/Mixed-Signal Simulation and SPICE Device Modeling
|
| Product |
Description |
Version |
| SmartSpice |
Parallel SPICE simulator |
4.44.3.R |
| SmartSpice Pro |
Fast Circuit Simulator |
4.44.3.R |
| SmartSpice RF |
Frequency and Time Domain RF Circuit Simulator |
4.44.3.R |
| SmartView |
Waveform viewer and simulation analysis |
2.34.11.R |
| Utmost IV |
Device characterization and SPICE modeling |
2.11.0.R |
| TechModeler |
Device modeling for new technologies using only device behavior |
2018.1.0.R |
| Spayn |
Statistical parameter and yield analysis tool for models and tests |
2.14.0.R |
| VarMan |
Variation-aware design solution |
2020.1.4.R |
Custom IC CAD
|
| Product |
Description |
Version |
| Gateway |
Hierarchical schematic editor |
3.8.10.R |
| Expert |
Hierarchical IC layout editor |
4.18.28.R |
| Guardian |
Physical verification of layout networks with DRC/LVS |
4.10.16.R |
| Hipex |
Full-chip parasitic extraction |
3.6.16.R |
Digital CAD
|
| Product |
Description |
Version |
| Silos |
Verilog simulator |
4.16.17.R |
| HyperFault |
Verilog IEEE-1364-2001 compliant fault simulator |
4.16.17.R |
| AccuCell |
Cell characterization and modeling |
3.0.12.R |
| AccuCore |
Block characterization, modeling and STA |
3.0.7.R |
| Spider |
Netlist-to-GDSII place-and-route design flow |
1.8.3.R |
Parasitic Extraction
|
| Product |
Description |
Version |
| Clever |
RC extractor for realistic 3D structures |
3.11.24.R |
| Exact |
Full-chip LPE rule file generator |
2.20.3.R |
| Quest |
3D RF passive device modeling |
2.0.10.R |
Extracted Netlist Analysis and Reduction
|
| Product |
Description |
Version |
| Jivaro |
RCLK parasitic reduction for post-layout netlist |
5.9.24 |
Power Integrity Signoff
|
| Product |
Description |
Version |
| Invar |
EM/IR, thermal reliability and power integrity analysis |
1.14.0 |
TCAD
|
| Product |
Description |
Version |
| Victory Process |
3D process and stress simulator |
7.46.3.R |
| Victory Device |
3D device simulator |
1.16.0.R |
| Victory Mesh |
Mesh integration between process and device or interconnect tools |
1.6.5.R |
| Athena |
1D and 2D process and stress simulator |
5.22.3.R |
| Atlas |
Device simulation of material-based devices |
5.30.0.R |
| Virtual Wafer Fab |
Perform Design of Experiments (DOE) and optimization experiments |
2.12.22.R |
| DeckBuild |
Create, edit and run TCAD simulation input files |
5.2.8.R |
| DevEdit |
Ceates and edit mesh structures for 2D or 3D simulators |
2.8.26.R |
| MaskViews |
Layout editor for GDS2 or Silvaco’s layout format |
3.2.26.R |
| TonyPlot |
Visualization tool for 1D and 2D TCAD structures |
3.10.24.R |
| TonyPlot 3D |
Visualization tool for 3D data from TCAD and parasitic extraction |
3.10.65.R |
| Radiant |
Design software for optoelectronic thin film devices |
1.4.0.R |
