High Density, Low Power Embedded Memory Compilers
Silvaco single port and dual port SRAM, 1 port and 2 port register file, and ROM memory compilers have more than 25 years of feature development. Silvaco compilers have been adopted and deployed at over 12 different foundries and IDMs worldwide. They are available in process nodes down to 22nm. Silvaco memory compilers are optimized for high density and low power and enable designers to achieve the optimal trade-off between performance, power, and area.
Silvaco memory compilers are extensively silicon proven, and provide high yield using variation-aware design tools and methodology.
Features and Benefits of All Memory Compilers
|Multiple Vt periphery||Customize memory compiler to targeted power, performance, area||●||●||●|
|Large voltage range||Dynamically select power vs frequency operation to control power consumption and performance||●||●|
|Embedded power switches||Saves SoC design time, area, and power while lowering risk||●||●|
|Segmented power control||Provides flexibility for segment power shut off and overall power management||●|
|Source biasing||Low power optimization||●|
|Read and Write Assist||Low voltage and low power operation||●|
|Multiple power management modes||Offers multiple power saving customization options||●|
|Single power supply option||Easy integration||●|
|Multiple Mux options||Provides flexibility for form factor and word sizes||●|
|Built in Redundancy option||Allows higher yield||●|
|Support for BIST (Built In Self Test) option||Support validation in manufacture||●|
Single Port, Dual port SRAMs and 1 Port and 2 Port Register Files
Silvaco’s single port and dual port SRAMs and its 1 port and 2 port register files have been designed to achieve minimum area and power while meeting aggressive timing requirements. These best-in-class memory compilers rely on smart architectures to provide optimal solutions to various design needs in terms of performance, power, and area combinations.
Power Management Modes
Multiple power modes for static power savings are available providing the flexibility to select the best trade-off between power saving and wake up time. Retention, retention-nap, and shut-down modes provide a progressive reduction of leakage power compared to stand-by mode.
Silvaco design architecture enables low power consumption through multiple compiler options.
Over 25 years of development has resulted in multiple patents for Silvaco ROM compilers. Thanks to its unique bit-cell and power-aware architecture, Silvaco’s ROM provides the best combination of high density and low power.
Compact Array Architecture
The compact programmable ROM array architecture (with a single programming layer) features high-speed memory read times enabled by reduced stray capacitance. Silvaco’s unique architecture enables reduced area with lower dynamic consumption compared to traditional ROM.
Ultra High Density, Multi-Bit Architecture
Silvaco technology features a multi-bit architecture and ultra-high-density cells that enables high-capacity ROMs. This patented architecture offers significant area reduction while keeping a reduced dynamic consumption compared to traditional ROM.
Multiple Foundry Support
- Adopted by multiple foundries
- Designed for re-targeting to other processes or foundries
- In production at multiple foundries with millions of wafers manufactured
- Designed with high-sigma variation analysis to ensure high yield in manufacturing (global and local variation) using Silvaco’s VarMan XMA variation analysis tool
- Supports major EDA tool flows
- Custom PVT support
- Fast and efficient technical support
For more information on Silvaco Memory IP contact Sales@silvaco.com or