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Silvaco at Upcoming Solid-State Conferences - ESSDERC 2020 and SISPAD 2020

Silvaco technologists and research partners will be participating in the ESSDERC/ESSCIRC 2020 joint conference for solid-state devices and circuits.  Tutorial #8, Ab-initio simulations supporting new materials & process developments, chaired by Denis Rideau (STMicroelectronics) and Philippe Blaise (Silvaco), includes a presentation by Dr. Tillmann Kubis of Purdue University. Dr. Kubis is working with Silvaco in the area of atomistic simulation.  He will present on  Atomistic Green’s functions: the beauty of self-energies.

CEO Perspective – Challenges and Opportunities for Global Semiconductor Businesses

by Babak Taheri, Silvaco CEO
In 1966 Robert F. Kennedy delivered a speech that mentioned a curse, “May you live in interesting times.” Like it or not, we live in an interesting time — a time of danger and uncertainty, but also a time of great possibilities.

Replay of 2020 ESD Alliance CEO Outlook Panel

The ESD Alliance CEO Outlook was held on June 17, 2020. This year’s informative event, featuring six prominent industry CEOs, was conducted as a virtual event, generously hosted by Arm. The panelists discussed the impact of COVID-19 on our industry, the rising cost of chip design, and many other topics.

Accelerating Design with the Victory TCAD Suite

The Simulation Standard, Silvaco’s technical journal for semiconductor process and device engineers is beginning its 30th year of publication. The latest issue has just been released and it outlines a complete power device design flow using the Victory suite of TCAD simulation solutions – Victory Process, Victory Mesh, and Victory Device.

TCAD Simulations of RF-SOI Switches with Trap-Rich Substrate

The market for cellular components has been shifting rapidly from GaAs pHEMT or silicon-on-sapphire (SOS) to silicon-based technology. CMOS (silicon-on-insulator) SOI antenna switches which are compatible with multimode GSM/EDGE, TD/WCDMA, and LTE systems exhibit higher integration levels and have become the fastest growing mobile phone submarket. CMOS-SOI processes, especially with thin silicon, have the potential to rival the FoM that was traditionally feasible only with GaAs technologies.

New MIPI I3C V1.1 Standard Streamlines Peripheral Connectivity with Lower Cost and Higher Bandwidth

The MIPI Alliance (MIPI) develops interface specifications for mobile and mobile-influenced industries. There is at least one MIPI specification in every smartphone manufactured today.

For Next Generation Nanowires, Simulation from Atoms to SPICE

As process nodes continue to shrink, the requirement for additional physics-based simulation is gradually creeping into each stage of the design process. By way of illustration, Technology Computer Aided Design (TCAD) simulations are becoming more atomistic in nature, SPICE models are becoming process aware to take account of localized strain effects, and back or middle end of line (BEOL or MEOL) parasitics are moving from exclusively two-dimensional (2D) rule-based solutions to full 3D structure field solvers for numerous critical sections of the layout.

Atomistic Analysis and Next Generation Computing at IEDM 2019

IEDM is THE device conference with more than a thousand participants from major companies and R&D institutes. Many talks were dedicated to new memory devices and circuits, including Ferroelectrics, MRAM, RRAM, driven by the requirements of AI processing. EUV is definitely there for 3nm and beyond. 3D integration was shown for LP-HP logic and RF. Gate-All-Around devices, with nanowires or nanosheets are mature versus FinFET.

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