• SmartSpice RadHard

SmartSpice RadHard Radiation Effects Circuit Simulator

SmartSpice RadHard provides simulation capability for modeling and analyzing radiation effects due to Single Event Effects (SEE), and Dose Rate (DR). Built upon the commercial SmartSpice Analog Circuit Simulator, it provides the accuracy, capacity and performance required to design and analyze the most advanced electronics and analyze the most advanced semiconductor technologies.

Key Features

  • Provides accurate Dose Rate (DR), SEE, analysis using the .RAD statement for transient and DC analysis
  • Built as an extension to industry-proven SmartSpice simulator
  • Analyzes DR with modified Wirth & Rogers’ models and with optional customer-defined models
  • Analyzes Single Event Upsets (SEU’s) and Multi-Bit Upsets (MBU’s) with modified Messenger’s models and with optional customer-defined models
  • Advanced circuit optimization improves the radiation tolerance of the your design and enables complex analysis of design trade offs necessary to meet system specifications
  • Supports standard foundry-supplied HSPICE®, PSPICE® and SmartSpice models for bulk CMOS, SOI, bipolar, an biCMOS processes
  • Provides open model development environment and extensive analog behavioral capability with Verilog-A option
  • Supports research of new and emerging phenomena through custom models and sophisticated ‘what if’ features in simulator control
  • SmartSpice RadHard is fully integrated into the Silvaco radiation tool flow which links process modeling, device simulation, circuit analysis, physical layout, and chip parasitic effects to deliver a high fidelity, physics based environment to assess radiation and reliability effects

Single Event Effects Analysis

  • Radiation physics incorporated through enhanced, fully complied versions of industry standard device models as opposed to subcircuits
  • Customer-defined current pulse modeling
  • Rapid, user friendly radiation effects analysis capability without complicating circuit netlists
  • Single bit upset analysis
  • Multi-bit upset analysis

Analog Custom Design Resources

Analog Simulation
Analog Custom Design & Analysis
SmartSpiceGateway
Model Generation
Guardian DRC
Utmost IVGuardian LVS
Parasitic Extraction
Expert
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Customers

Cameron Fisher
 MSC has found SmartSpice™ to be an excellent value in terms of easy integration, debug run time and total cost of simulation. Support during our learning curve has been great. MSC will be using SmartSpice™ for all future memory complier development.