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Simulation Standard

A Journal for Process and Device Engineers

The SmartSpice Interface to Cadence (revisited)

The SmartSpice interface to the Cadence Design Framework II has been substantially improved in its latest release (version 1.0.8.R), following feedback from a number of existing users.

CellRATER from Taveren Technology fast, Accurate Cell Library Characterization for Deep Submicron Timing Flow Improvement

Taveren Technology, Inc., a startup company based in Austin, Texas is busy developing the next generation performance characterization tool suite.

Cell Characterization with .MODIF Statement in SmartSpice

SmartSpice provides many unique and powerful features to facilitate parametric analysis in general and cell characterization in particular.

Local Optimization Templates for Extracting BSIM3v3.1 Parameters in UTMOST III

The BSIM3v3.1 SPICE model has become an industry standard for modeling deep-submicron MOS technologies. The model is suitable for both digital and analog applications because of the better modeling of the output conductances and the physics based scaling which is embedded in the model equations.

Hints, Tips, and Solutions – January 1998

Q: What is typical measurement set-up for the S3245A Noise Amplifier and what measurement equipment is used?A: Typical Measurement Set-Up

Simulation Standard

A Journal for Process and Device Engineers