• Technical Library

Simulation Standard

A Journal for Process and Device Engineers

BSIM3SOI Level=25 Model Released in SmartSpice

The Berkeley BSIM3SOI model, released in December 1997, is now available within SmartSpice as the MOSFET level=25 model. This model incorporates three separate implementations: the original Berkeley model implementation is invoked with the selector Berk=2; the Silvaco implementation is invoked with Berk=-2.

Scanbox Approach to Shape Reconstruction for Automated Reticle Inspection

The paper describes a generalization of the scanline approach [1] to reconstruction of the shape of planar object represented by a discrete point set with a given distance threshold d. This problem arises in applications of VLSI layout image processing, e.g., during automated reticle inspection.

Savage Enhanced with Recognition and Reporting of Hierarchical Structure of Errors

This article describes a method of reporting DRC errors implemented in Savage, applicable to multi-million transistor layouts. The method of hierarchical information inheritance is a perspective approach in an extension of capabilities of flat DRC systems. This technique makes it possible to report hierarchical errors in ordinary flat DRC systems.

Circuit Verification via Hypergraph Realization

One of the most challenging and time consuming tasks in VLSI design automation is Layout Versus Schematic (LVS). The problem is to test the consistency between the actual circuit, represented by the layout, and the nominal circuit upon which the design was based.

HINTS & TIPS – March 1998

Q: Is it possible to perform a DRC check on portions rather than on the whole circuit useful when only 2 or 3 errors to fix ?

3D Simulation of Power Devices Using Giga3D and MixedMode3D

Recent additions to the ATLAS device simulation framework have added the ability to simulate 3D electrothermal effects in Giga3D and mixed circuit simulation with 3D device simulation in MixedMode3D. The new modules add to the existing 3D device simulation within ATLAS as shown in Figure 1.