Models : Devices and operation Examples
- 001_asrc_g-element : Voltage-Controlled Current Source (G Element)
- 002_N_element_noise_source : N element noise source, to probe circuit.
- 003_complex_sources : Modulated sources as single element in circuit.
- 004_verilog-a_res : Verilog-A simple Resistor Chain
- 005_verilog-a_cap : Verilog-A simple Capacitor
- 006_ibis_buffer : IBIS Buffer
- 007_runtime_expression : Runtime Expression evaluation
- 008_soa_operation : Safe Operating Area (SOA) opration
- 009_process_corners : Simulating over Process corners
- 010_encryption : Encryption of Models for IP protection
- 011_hierarchical : Inverter-equivalent Design (4-Bit Carry Look Ahead Adder)
Additional Info:
These examples are for reference only. Every software package contains a full set of examples suitable for that version and are installed with the software. If you see examples here that are not in your installation
you should consider updating to a later version of the software.