/wp-content/uploads/2019/11/silvaco-logo.png00Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2022-01-21 13:27:142022-02-10 14:16:20Managing the Complexity of FinFET Standard Cell Layout with Cello
/wp-content/uploads/2019/11/silvaco-logo.png00Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2021-08-17 09:06:282021-09-10 10:01:00Designing with Silvaco’s Octal SPI Memory Controller with Advanced Memory Support for IoT Systems
/wp-content/uploads/2019/11/silvaco-logo.png00Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2021-06-03 14:18:592021-06-26 08:14:54Achieving Extreme Low Power IoT Designs with Silvaco’s 55LPx Foundation IP Solution
/wp-content/uploads/2019/11/silvaco-logo.png00Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2022-02-24 11:00:212022-05-24 11:13:23Silvaco’s Dr. Firas Mohamed Elected to Co-chair of Si2 Artificial Intelligence/Machine Learning Special Interest Group
/wp-content/uploads/2019/11/silvaco-logo.png00Erick Castellon/wp-content/uploads/2019/11/silvaco-logo.pngErick Castellon2020-12-09 00:00:282020-12-08 15:40:49Silvaco and OPENEDGES Announce Availability of Integrated DDR Controller and PHY IP Solutions
https://silvaco.com/wp-content/uploads/2020/04/design-ip.jpg500500Ingrid Schwarz/wp-content/uploads/2019/11/silvaco-logo.pngIngrid Schwarz2019-08-09 17:20:362020-12-22 16:30:52Everything You Want to Know about Silvaco Foundation IP
Over the past two years, Silicon Catalyst has been working with key industry players to develop a complete ecosystem that economically and effectively supports the new wave of semiconductor startups that we are seeing today. Our Portfolio Companies have consistently been requesting IP as the critical element that we had not been able to deliver. Silvaco’s offering fulfills a real hole that has been impeding the success of these startups. We are glad to deliver this capability as we continue to build the semiconductor start up ecosystem.
The integrated solution enables design teams to collaborate efficiently in a secure design environment when developing their IPs or SoCs either locally or across multiple design sites. It enables design teams to successfully tapeout their designs by mitigating the risk by sharing and using the correct version of the design data and IPs.
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