005_verilog-a_cap : Verilog-A simple Capacitor

Requires: SmartSpice & Smartview

Minimum Versions: SmartSpice 3.6.8.R

This example shows how to implement a capacitor in Verilog-A and compares the waveform in a simple circuit transient simulation with a native spice element.

The Verilog-A input deck consists of a sinewave voltage source into a series resistor then a parrallel connection of capacitor and resistor to ground. In this case the capacitor element is from a Verilog-A file. A plot shows the input and output simulated waveforms.

Next the spice input deck which is the same circuit but this time with a standard spice capacitor element can be simulated. This plot shows a similar output waveform.

Comparing the 2 simulation waveforms we can see a good agreement between the 2 inplementations of the capacitor element.