Analog Cores - Silvaco

Silvaco offers a suite of high-performance and low-power analog IP solutions for Samsung Foundry.

Title	Features	Samsung Foundry
Title	Features	28nm FD-SOI	14 nm	11 nm	10 nm	8 nm	7 nm	5 nm*
Integer PLL	1.2 GHz
	2.0 GHz
	2.4 GHz
	2.5 GHz	√
	3.2 GHz
	4.3 GHz
	4.5 GHz				√	√
	6.6 GHz						√	√
Fractional-N SSC PLL	1.2 GHz
	2.5 GHz	√
	3.2 GHz
	4.5 GHz				√	√
	6.6 GHz						√	√
Low Jitter PLL	100 MHz
Low Jitter PLL	640 MHz
ADC	12 bit, 1.0 MSPS, 16-ch
ADC	12-Bit 320 MS/s Dual ADC
DAC	12 bit, 640 MSPS
Oscillators	1.0 MHz
	49.152 MHz
	200 MHz		√
	300 MHz to 700MHz
	400 MHz						√	√
Regulators	3.3V to 1.8V 350mA
	1.8V to 0.8V 100mA
	1.8V to 1.2V 200mA
	1.8V to 0.9V 250 mA
	1.35V to 0.85V 220mA LDO				√	√
	1.2V to 0.8V 550mA
	1.8V to 0.9V 45mA
	1.8V to 1.2V 500mA
	1.8V to 0.75V 10mA LDO					√
	1.8V to 1.2V 20mA LDO						√	√
	1.8V to 0.75V 80mA LDO						√	√
POR	0.75V Power On Reset				√	√	√	√
	0.8V Power On Reset
	1.0 V Power on Reset	√
ABBG	Adaptive Body Bias Generator	√
Detectors	Droop				√	√	√	√
	Low Voltage, 1.8V / 0.8V
	Low Voltage, 1.8V / 1.2V / 0.8V		√
Temperature Sensors	-40 to 125°C, Resolution: 0.0625°C
	-40 to 125°C, Resolution: 0.5°C						√	√
	-40 to 125°C, Resolution: 1°C				√	√
PVT Sensors	Process, Voltage and Temperature sensor. RVT (Regular Vt ) / LVT (Low Vt) process sensor type, 0 to 1.3V, -40 to 125°C, Resolution: 0.0625°C
Audio Codec	24-Bit 48KHz
Attack Detectors	Laser Attack
	Voltage Supply Attack
	Temperature Attack
	Frequency Attack

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Customers

Rick Lazansky

Over the past two years, Silicon Catalyst has been working with key industry players to develop a complete ecosystem that economically and effectively supports the new wave of semiconductor startups that we are seeing today. Our Portfolio Companies have consistently been requesting IP as the critical element that we had not been able to deliver. Silvaco’s offering fulfills a real hole that has been impeding the success of these startups. We are glad to deliver this capability as we continue to build the semiconductor start up ecosystem.

Silicon Catalyst

CEO

Srinath Anantharaman

The integrated solution enables design teams to collaborate efficiently in a secure design environment when developing their IPs or SoCs either locally or across multiple design sites. It enables design teams to successfully tapeout their designs by mitigating the risk by sharing and using the correct version of the design data and IPs.

ClioSoft

CEO

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