Foundation IP for 180nm to Sub-12nm Process Nodes
Silvaco offers a complete portfolio of Foundation IP for the creation of ASICs and SoCs for almost any process node:
- Standard Cell Libraries for digital logic
- I/Os, for general and specialty purposes, and ESD structures
- Memory Compilers for SRAMs, ROMs, and register files
Silvaco Foundation IP gives a significant improvement in both power and area.
For over twenty years, Silvaco has been providing Foundation IP to the design community. Silvaco is committed to offering best-in-class components and a full set of services: a one-stop shop for chip developers and foundries.
Legacy Standard Cell Libraries
There are several established foundries for mature process nodes at 110nm and above. These mature processes have been in the market for over twenty years. The standard cell libraries that were developed earlier do not include recent technology developments. They can be improved for power footprint, performance, and area by employing:
- Tapless architecture
- Clock gating
- Vt variants
- Power management kits (PMK) & multi-power islands
- Multi-bit FFs
- Fine grain sizing
- Complex function matching
Silvaco IP Standard Cell Foundation IP
With 700 to 1,200 standard cells, multi VTs and track heights, the Silvaco standard library offers thousands of cell variants, enabling applications from ultra-low power to high speed. Silvaco carefully sizes each cell family in the library, optimizing transistor sizes, P/N ratios, and drive strength granularity for further power and performance gains.
Cello, Silvaco’s EDA platform for layout optimization, enables a new level of optimization, with 35% area and 20% power reduction compared to off-the-shelf libraries from other vendors. Multi-bit and multi-height standard cells boost routing density even further by reducing pin count and packing more functionality inside standard cells. For example, the detailed review and exploration of 28nm design rules by Silvaco engineers resulted in the creation of an ultra-high density low-power library with a gate density of four million gates per square millimeter, the maximum possible for that node.
Silvaco Foundation IP libraries support multiple foundries, multi-VT, and multi-bit FFs. They come with standard and custom PVT corners. For each library, add-ons include power management kits (PMKs) and ECO kits with fixed pattern for FEOL layers. Through the Cello platform, library creation, migration, and optimization services are available down to 7nm process nodes. Off-the-shelf libraries targeted specifically to different foundries include:
- 6/7/9/10/12 track libraries for the 180/152nm, 130/110nm, 90/80nm, and 65/55nm process nodes
- 7/8/9/10/12 track libraries for the 40nm and 28/22nm nodes
To use a Silvaco Foundation library, contact Sales@silvaco.com or request it from your foundry.
For more information on Silvaco standard cell library Foundation IP, contact Sales@silvaco.com or