Silvaco IP offers production-proven high-speed interface IP solutions for Samsung Foundry. Items marked AQ are AEC-Q100 qualified and ASIL assessed for automotive applications.
| Protocol | Features | Samsung Foundry | ||||||
|---|---|---|---|---|---|---|---|---|
28nm FD-SOI | 14 nm | 11 nm | 10 nm | 8 nm | 7 nm | 5 nm* | ||
| PCIe | PCIe Gen 3, 8 Gbps |  | | |||||
| PCIe Gen 3/4, 16 Gbps | | | | | ||||
| DDR | DDR3/4, 3.2 Gbps, 32/64-bit | | | | ||||
| LPDDR3/4, 4.3 Gbps, 16/32-bit | | | | |||||
| DDR/LPDDR3 Combo, 1.6 Gbps, 32-bit | | | ||||||
| LPDDR4/4X, 4.3 Gbps, 16/32-bit | | | | | ||||
| LPDDR4/4X/5, 5.5 Gbps, 16-bit | | |||||||
| LPDDR4/4X/5, 6.4 Gbps, 16-bit | | | | | ||||
| HBM2e, 3.2 Gbps | √ | √ | ||||||
| MIPI | M-PHY G3, 6.0 Gbps (UFS only) | | | | | |||
| M-PHY G4, 12.0 Gbps (UFS only) | | | | | | |||
| D-PHY V1.2, 2.1 Gbps | | | ||||||
| C-PHY D-PHY Combo V1.1 (2.5 Gbps) / V1.2 (2.5 Gbps) | | |||||||
| C-PHY D-PHY Combo V1.1 (2.5 Gbps) / V2.0 (4.5 Gbps) | | | | | ||||
| SerDes | SerDes 56 Gbps, 10/50G-KR, 100G-KR2/4, 200G-KR4 | | | |||||
| HDMI | HDMI 2.0 Tx, 6.0 Gbps | | | |||||
| USB / DisplayPort Combo | USB 3.1 Gen 1 / DP Tx Combo, 5 Gbps / 5.4 Gbps | | | | | |||
| V-by-One | Tx, 4 Gbps, 16 lanes | | | |||||
| Rx, 4 Gbps, 8 lanes | | | ||||||
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Rick Lazansky
Over the past two years, Silicon Catalyst has been working with key industry players to develop a complete ecosystem that economically and effectively supports the new wave of semiconductor startups that we are seeing today. Our Portfolio Companies have consistently been requesting IP as the critical element that we had not been able to deliver. Silvaco’s offering fulfills a real hole that has been impeding the success of these startups. We are glad to deliver this capability as we continue to build the semiconductor start up ecosystem.
Srinath Anantharaman
The integrated solution enables design teams to collaborate efficiently in a secure design environment when developing their IPs or SoCs either locally or across multiple design sites. It enables design teams to successfully tapeout their designs by mitigating the risk by sharing and using the correct version of the design data and IPs.
ClioSoft
CEO
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