Entries by Erick Castellon
Atomistic Analysis and Next Generation Computing at IEDM 2019
IEDM is THE device conference with more than a thousand participants from major companies and R&D institutes. Many talks were dedicated to new memory devices and circuits, including Ferroelectrics, MRAM, RRAM, driven by the requirements of AI processing. EUV is definitely there for 3nm and beyond. 3D integration was shown for LP-HP logic and RF. Gate-All-Around devices, with nanowires or nanosheets are mature versus FinFET.
TCAD Recommended Textbooks
CMOS: Mixed-Signal Circuit Design, Second Edition R. Jacob Baker. Published Wiley-IEEE Press, 2nd Edition. Published 2009, pp. 330 ISBN 978-0-470-29026-2 Understanding Modern Transistors and Diodes David L. Pulfrey, Cambridge University Press, New York, 2010, pp. 336 ISBN 978-0-521-51460-6 Understanding Signal Integrity Stephen C. Thierauf, Published Artech House, December 2010, pp. 250 ISBN-13: 978-1-59693-981-3
Customer Case Study: Using SmartSpice to Deliver Next-Generation, Low Power Memory Systems
At our SURGE Santa Clara event in October, Cameron Fisher, CEO of Mobile Semiconductor described their experience in adopting SmartSpice as their characterization engine for creating the database for their Trailblaze™ memory compiler software. Below is a summary of his talk.
Silvaco Exhibits and Presents Invited Paper on Atomistic Simulation at IEDM 2019
The IEEE International Electron Devices Meeting (IEDM) is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. It is the flagship conference for
Nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices
Novel quantum and nano-scale devices and phenomenology
Optoelectronics, devices for power and energy harvesting, high-speed devices
Process technology and device modeling and simulation
Next Generation CMOS Nanowire: From Atoms to Circuit Simulation
Abstract— A complete simulation flow for a Nanowire-based ring oscillator circuit is presented, where the active devices were simulated using an atomistic device simulator. The results of this simulation have been fitted to an active device SPICE compact model, specifically formulated for nanowire/Gate all around Field Effect Transistors” (FETs). Finally, the active devices were incorporated into a SPICE netlist including back end resistance and capacitance parasitics.
Optimization of Select Gate Transistor in Advanced 3D NAND Memory Cell
Abstract—There are several device challenges unique to the select gate transistor in 3D NAND memory cell. It requires low leakage current to prevent read and program disturb problems and it needs to provide enough current during read and erase operation. In this paper, we examined the design optimization of select gate transistor with respect to various device elements including work-function, S/D overlap, and trap density. Finally, we reviewed the path to reduce the channel length of the select gate transistor in conjunction with the role of dummy cells.
RFSOI Switch Harmonics Simulations with Trap-Rich Substrate
In this paper, in order to understand trap-rich substrate behavior, passive and active device on SOI with trap-rich layer structures were simulated using the Victory Device simulator. Harmonics distortion of devices were also compared.