AI and Machine Learning SoCs – Memory and Interconnect IP Perspectives
This webinar will discuss the challenges of developing of artificial intelligence (AI) and machine learning (ML) based SoCs. Novel architectures for AI and ML applications are needed to meet efficiency requirements. These include specialized processing, high bandwidth and low-energy memory throughput, and reliable high-performance connectivity. We will present the efficient customization of memory and interconnect IPs for successful development of AI and ML SoCs.
What attendees will learn:
- Challenges of AI/ML SoCs
- Key requirements of Memory and Interconnect IPs for AI/ML SoCs
- Memory and interconnect SIPware solutions by Silvaco
Ahmad S. Mazumder is a principal field application engineer in IP Engineering division of Silvaco. He is responsible for development and customer support in all analog and interface IPs. He is an industry veteran on the development of high-speed memory, interface IPs, and many types of analog IPs. He worked on cutting edge DDR, extreme high-speed SerDes, interfaces, ESD, and QoR for 24 years at various SoC companies (Intel, Broadcom, C-Cube Microsystems, etc). He recently joined Silvaco’s IP Engineering division.
Ahmad S. Mazumder holds a MS in VLSI Semiconductor Design from the City University of New York and BS in Electrical and Electronics Engineering from Bangladesh University of Engineering and Technology.
When: December 6, 2018
WHO SHOULD ATTEND:
Academics, engineers, and management looking for solutions to design and optimize artificial intelligence and machine learning SoCs.