February 16, 2023
In this webinar, we will share the challenges of optimizing and validating different libraries, and demonstrate how Cello, Viola, and SmartSpice contribute in a unique and dynamic way to realize fast and accurate optimization and characterization.
https://silvaco.com/wp-content/uploads/2023/01/Webinar-Image_Feb16.jpg335625Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2023-01-23 11:09:002023-05-23 09:46:02Learn How SilTerra Uses Cello and Viola for Standard Cells and I/O Library Optimization and Characterization
May 12, 2022
In this webinar, we will provide an overview of the AMBA AHB subsystems and products offered by Silvaco. Some topics of discussion include Channel vs. Fabric architecture, low power, customization, hardware- and software-based security, and co-verification of the hardware and software.
/wp-content/uploads/2019/11/silvaco-logo.png00Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2022-04-26 08:02:462022-07-01 12:52:54Learn About Silvaco’s AMBA AHB Subsystems and How to Customize, Secure, and Verify
February 10, 2022 | 10:00 am – 10:30 am (PST)
In this webinar we are going to review some of the most challenging aspects of FinFET standard-cell layout design, and how Silvaco’s Cello tool can be used to address these issues.
/wp-content/uploads/2019/11/silvaco-logo.png00Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2022-01-21 13:27:142022-02-10 14:16:20Managing the Complexity of FinFET Standard Cell Layout with Cello
September 9, 2021 | 10:00 am – 10:30 am (PDT)
This webinar will focus on a specific class of memory devices – targeted to mobile and IoT applications – that use “SPI” (Serial Peripheral Interface) signaling.
/wp-content/uploads/2019/11/silvaco-logo.png00Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2021-08-17 09:06:282021-09-10 10:01:00Designing with Silvaco’s Octal SPI Memory Controller with Advanced Memory Support for IoT Systems
June 24, 2021 | 10:00 am – 10:30 am (PDT)
In this webinar you will learn how Silvaco Foundation IP helps you achieve your low power designs Memory compiler features and flexibility Standard Cell library features and implementation.
/wp-content/uploads/2019/11/silvaco-logo.png00Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2021-06-03 14:18:592021-06-26 08:14:54Achieving Extreme Low Power IoT Designs with Silvaco’s 55LPx Foundation IP Solution
January 28, 2021 | 10:00 am – 10:30 am (PST)
In this webinar you will learn how Rafael Microelectronics has deployed Silvaco’s AMBA subsystem in their latest IOT design. Rafael Microelectronics develops high frequency broadband RF IC designs and narrow band IOT IP and devices. Rafael recently created a new wireless IOT SoC employing Rafael’s Bluetooth/Zigbee/Sub-GHz RF IP, leveraging Silvaco’s ABMA subsystem IP.
/wp-content/uploads/2019/11/silvaco-logo.png00Erick Castellon/wp-content/uploads/2019/11/silvaco-logo.pngErick Castellon2021-01-18 08:55:572021-01-28 14:36:28Accelerating Wireless IOT SoC Implementation with Silvaco AMBA® Subsystem IP
February 23, 2021 | 10:00 am – 10:30 am (PST)
This webinar presents Silvaco’s Embedded Memory offerings as part of a complete Foundation IP suite that includes Standard Cells and IO’s.
/wp-content/uploads/2019/11/silvaco-logo.png00Erick Castellon/wp-content/uploads/2019/11/silvaco-logo.pngErick Castellon2021-01-17 22:49:162021-03-03 15:04:09How to Design Ultra-low Power Embedded Memories with Silvaco Memory Compilers
January 14, 2021 | 10:00 am – 10:20 am (PST)
In this webinar, Sharmistha Sinha and Anand Mishra share their analysis and experience with Cello done at ST on multiple technologies.
/wp-content/uploads/2019/11/silvaco-logo.png00Erick Castellon/wp-content/uploads/2019/11/silvaco-logo.pngErick Castellon2020-12-14 16:06:532021-01-18 08:57:13Reducing the Layout Development Cycle Time for Standard Cells
October 13, 2020 | 10:00 am – 10:30 am (PST)
As computation requirements continue to build and memory systems are operating at ever higher frequencies, high-performance memory subsystems that consume minimal power consumption and small silicon area are a necessary requirement.
/wp-content/uploads/2019/11/silvaco-logo.png00Erick Castellon/wp-content/uploads/2019/11/silvaco-logo.pngErick Castellon2020-09-03 20:58:192020-12-14 16:36:45Choosing the Right DDR Memory Subsystem for Your Next SOC!
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