• Simulation Standard Technical Journal

Simulation Standard Technical Journal

A Journal for Process and Device Engineers

Quantum Modeling Part I: Poisson-Schrodinger Solver

The trend toward smaller MOSFET devices with thinner gate oxide and greater doping is resulting in the increased importance of quantum mechanical effects, which are observed as shifts in threshold voltage and gate capacitance. Predicting these quantum effects requires solving the Schrodinger equation. This article (part 1 of a series) presents the Poisson-Schrodinger solver and its enhancements implemented in ATLAS from Silvaco.

Simulation of a High Gain InP/InGaAs/InP Double HBT with Varying Doping Profile within ATLAS

It is possible to now create new heterojunction and double heterojunction bipolar transistors [2] utilizing junction layers made of different heterojunction semiconductor materials. Typically a heterojunction bipolar transistor (HBT) consists of a hetrojunction at the base-emitter junction and a homojunction at the base-collector junction. A double hetrojunction bipolar transistor (DHBT) is made of two heterojunctions, both at the base-emitter and at base-collector junctions.

Order of Multiple Implants in a Process Affects Results

When an implant occurs there will be some level of damage to the crystal structure of the silicon. If this damage is not annealed out then any subsequent implant will have a different penetration depth compared with the crystal that has no damage. The reason this occurs is due to the crystallographic nature of silicon. This means that there are some "channels" along certain crystallographic directions where ions can move much more freely.

Temperature Effects in SmartSpice LEVEL=6 Ferroelectric Capacitance Model From Ramtron

Implementation of a new ferroelectric capacitance model from Ramtron International Corporation into SmartSpice was first described in the April 2002 issue of Silvaco Simulation Standard. This model utilizes a new concept of double distribution of domain reversal voltages. The temperature effects were not detailed in the previous article. This application note discusses the implementation of the temperature effects and updates the device syntax.

UFSOI V7.0 (UFPDB V2.0) Model Released in SmartSpice

Version 7.0 of the University of Florida Silicon-On-Insulator (UFSOI), released in 2002, is now available with Silvaco SmartSpice by setting LEVEL to 21. SmartSpice uses version 7 by default, but versions 4.5, 5.0, 5.0 rev 1.0, and 5.0 rev 6.0 are still available through resetting the VERSION and REVISION parameters.

Managing SmartSpice / SmartView Simulation Output Raw Files

Silvaco SmartSpice simulation results are typically stored in RAM. Since transient simulations of large circuits often exceed 1GB, a large swap-space partition is required prior to simulation. Constant disk access may dramatically decrease simulation speed, therefore shifting some or all of the load to the system’s memory helps to alleviate this problem.