• Simulation Standard Technical Journal

Simulation Standard

Technical Journal

A Journal for Process and Device Engineers

Order of Multiple Implants in a Process Affects Results

When an implant occurs there will be some level of damage to the crystal structure of the silicon. If this damage is not annealed out then any subsequent implant will have a different penetration depth compared with the crystal that has no damage. The reason this occurs is due to the crystallographic nature of silicon. This means that there are some "channels" along certain crystallographic directions where ions can move much more freely.

Temperature Effects in SmartSpice LEVEL=6 Ferroelectric Capacitance Model From Ramtron

Implementation of a new ferroelectric capacitance model from Ramtron International Corporation into SmartSpice was first described in the April 2002 issue of Silvaco Simulation Standard. This model utilizes a new concept of double distribution of domain reversal voltages. The temperature effects were not detailed in the previous article. This application note discusses the implementation of the temperature effects and updates the device syntax.

UFSOI V7.0 (UFPDB V2.0) Model Released in SmartSpice

Version 7.0 of the University of Florida Silicon-On-Insulator (UFSOI), released in 2002, is now available with Silvaco SmartSpice by setting LEVEL to 21. SmartSpice uses version 7 by default, but versions 4.5, 5.0, 5.0 rev 1.0, and 5.0 rev 6.0 are still available through resetting the VERSION and REVISION parameters.

Managing SmartSpice / SmartView Simulation Output Raw Files

Silvaco SmartSpice simulation results are typically stored in RAM. Since transient simulations of large circuits often exceed 1GB, a large swap-space partition is required prior to simulation. Constant disk access may dramatically decrease simulation speed, therefore shifting some or all of the load to the system’s memory helps to alleviate this problem.

Defining Voltage Controlled Oscillators in SmartSpice

One of the methods to define a Voltage Controlled Oscillator (VCO) in a SPICE simulation is to make use of a voltage-controlled voltage source (E element). A typical VCO expression makes use of a sinusoidal function as shown in Formula 1.

Geometry Binning for TFT models and SmartSpice Tips

Level=36 RPI poly-Si TFT and other original TFT models do not support automatic geometry binning. The enhanced model included with SmartSpice 1.9.7.C or later now supports the selecting of a suitable model with both LMIN/LMAX and WMIN/WMAX, as well as with other MOSFET models.