One of wide bandgap semiconductors, SiC has been widely applied to the power devices, and then, the super-junction MOS transistor of SiC is being investigated to obtain higher performance for Ron and BV [1]. The super-junction structure is fabricated by trench filling with the epitaxial growth [2, 3].

Gallium nitride (GaN)-based devices for power electronics show superior performance in comparison to silicon carbide and silicon-based devices [1]–[3]. The development of vertical devices, like pn-diodes and power HEMTs results in higher power density and voltage handling. One of the key parameters of this technology is the dislocation density. This is lower in free-standing GaN-on-GaN epitaxy than in heteroepitaxial GaN growth on different substrates like SiC or Si, but still has a density of 104-106 cm-2 [4]. The diode reverse leakage seems to be related to the dislocation density, and it can be modelled with a Poole-Frenkel or a hopping conduction mechanism [5]. The Poole-Frenkel model is already implemented in the trap-assisted tunnelling model in Silvaco Atlas [6]. For the leakage in threading dislocations a variable-range hopping (VRH) model has been implemented in the simulator, based on Ref. [7].