Simulation Standard

MOS31 JFET/MOSFET Model Now Available in SmartSpice

July 2, 1999

Silvaco now offers the MOS31 JFET/MOSFET model originally developed by Philips [1] as part of the SmartLib product-independent model library. This model is available within SmartSpice as level 31.

New SOI UTMOST Module

July 1, 1999

Bulk CMOS is currently the dominant technology for VLSI integrated circuits but its scaling constraints pose ever greater as device geometries shrink. Thus, the search for a suitable replacement has begun, and Silicon-On-Insulator (SOI) technology seems to become the most attractive candidate for a suitable VLSI/CMOS technology.

Hints & Tips May 1999

June 4, 1999

A. Previous articles in the Simulation Standard have highlighted the diffusion models required for accurate simulation of shallow source/drain junction formation[1] and Reverse Short Channel Effect (RSCE)[2][3]. However for complete simulation of MOS short channel behavior it is necessary to consider the diffusion of the channel implants before the source/drain processing.

Hints & Tips June 1999

June 2, 1999

Q: I want to draw several long wires, with precise positioning of both ends. I am used to doing this as follows:

Maverick- Hierarchcal Full-Chip Extractor Recent Significant Advances

June 1, 1999

Maverick is a sophisticated full chip hierarchical netlist extractor [1]. It augments the existing CELEBRITY framework which includes state-of-the-art software for VLSI layout editing, hierarchical design rule checking and layout versus schematic comparison. The latest release of Maverick is equipped with many new interface features, including the ability to search for a net by name, and new engine upgrades, such as extraction of parameters of active devices. A new numerical procedure has been developed for resistance extraction of complex geometrical shapes.

Circuit Performance Analysis of Multiple ATHENA Transistors Using MixedMode

May 3, 1999

In a previous issue of Simulation Standard for Process and Device Engineers[1] the simulation of a three stage CMOS ring oscillator using ATLAS/MixedMode was introduced. The MOSFETs used in the MixedMode simulation were created using analytical doping profiles specified within ATLAS. This article is intended to investigate some of the effects of process variation on ring oscillator performance. Thus, the individual devices in the ring oscillator circuit are created usingthe two-dimensional process simulation program, ATHENA.