• Simulation Standard Technical Journal

Simulation Standard Technical Journal

A Journal for Process and Device Engineers

Advanced Pairwise Merging Algorithm for VLSI Floorplanning

This paper concerns the problem of determining optimal placement of rectangular blocks within a rectangular area known as the packing or cutting-stock problem. This problem arises at then floorplanning stage of VLSI design.

Introducing Guardian – LVS Verification for PC-based Platforms

Guardian is a (state-of-the-art) hierarchical netlist comparison system, which eliminates many of the disadvantages of existing programs. Running on PCs under Windows NT, it easily compares circuits with a large number of devices. The advanced algorithms implemented in Guardian allow a substantial reduction of execution time and also detect discrepancies between two netlists more precisely. Guardian generates a comprehensive hierarchical report, which is easy to read. An embedded tool, called the Spice Netlist Rover, links report files with source netlists to make inspecting correct matches and errors simple.

Mixed Circuit Device Simulation of Single Event Upset in a Memory Cell

This article presents Single Event Upset (SEU) simulation of a SRAM cell using MixedMode3D. MixedMode3D provides the capability to simultaneously perform circuit simulation coupled with three-dimensional device simulation. This allows one to examine the internal operation of a three-dimensional numerically simulated device and predict the response of the attached circuit in a self consistent manner.

New, Fast Numerical Algorithm for Diffusion Modeling Implemented in ATHENA Version 5.0

A new diffusion algorithm based on a Galerkin method with linear finite elements, an extremely fast sparse matrix solver, and object oriented physical modeling is one of the new features implemented in ATHENA version 5.0. This module is an alternative to the existing code, thus providing the user with a choice between using the old diffusion module and the new algorithms.

Hints & Tips January 1999

A. Typically, UTMOST III s-parameter module is used to measure the FT versus IC (collector current) characteristic of bipolar transistors. The FT_CE routine can also be utilized to extract important parameters such as Fmax, Gmax, Upg and K factor. These parameters provide a clear indication of the performance of the device as an amplifier.

New Parameters for TFT model: Amorphous (Level=35) and Poly-Silicon (Level=36) TFT

Several enhancements have been made to the TFT models in SmartSpice. New parameters have been added to improve accuracy and allow simular sophisticated modeling options to MOS.