Jivaro Parasitic Reduction for Fast, Accurate Simulation
Jivaro is a unique stand-alone solution dedicated to the reduction of parasitic networks. It helps back-end verification teams speed up post-layout SPICE simulation of huge extracted parasitic circuits, while keeping high accuracy.
Jivaro has proven to dramatically accelerate circuit simulation while preserving high accuracy. It has been adopted at leading IDM companies and fabless worldwide for technology nodes from 65nm down to 7nm. Jivaro applies a patented mathematical approach to perform Model Order Reduction (MOR) to reduce parasistic complexity. In contrast to rule based methods, Jivaro allows the trade off of accuracy and reduction, with the user controlling the benefits.
Jivaro is a reduction tool independent of the extractor and the simulator. As a tool dedicated to reduction, it allows complete adaptability to the flow and the type of designs or challenges, providing a single solution for all cases.
Jivaro can be applied with different thresholds on different parts of the design to optimize reduction. It can also offer more than MOR through the reduction of the number of active devices. It can deal with all netlist types, including power nets, and can reduce designs with hundreds of parasitics in a single net.
- Accepts R, RC, RCC, RLC, RLCK, controlled sources
- Supports DSPF, SPEF, SPICE3, HSPICE®, SPECTRE®, Calibre® View, OA databases
- Reduces temperature-dependent parasitic networks and multi-corner extracted netlists
- Can be applied differently on selected nets, sub-circuits or path within the hierarchy
- Merge of multi-finger active devices
- Supports negative resistors
- Graphical user interfaces to pilot the reduction options or inline binaries for batch runs
- Compatible with all major EDA tools