• Parasitic Extraction Examples

    Utmost IV Examples

clex21.in : Calculating Well Isolation and Source/Drain Capacitance

Requires: CLEVER Version 3.6.10 or Later

This example demonstrates how to:-

  • Include well isolation depletion capacitance in the calculation.
  • Include source/drain depletion capacitance in the calculation.
  • Specify cyclical cell boundary conditions for emulating cascaded cells.

Including Well Capacitance in the Field Solver Parasitic Extraction

Diode isolated wells can be treated as a separate volume of silicon that is separated from the bulk wafer by a layer of insulator where the insulator thickness is the silicon depletion width and the insulator has the same permitivity as silicon.

For a first order calculation, the depletion width of a diode separated well or source/drain region increases with the square root of the doping concentration of the lowest doped side of the junction. If you don't know the depletion width of the junctions, a good approximation can be obtained from the following formula:

Depletion Width (um) = SQRT ( 1e15 / Doping )

where the Doping is the volume doping of the lightly doped side of the junction in atoms/cm3. So for 1e15/cm3 doping, use 1um, for 1e17/cm3, use 0.1um and for 1e19/cm3 use 0.01um etc.

In this example, the depletion region of the N-Well is simulated by first etching the silicon to the depth of the N-Well in the masked N-Well regions, and then by depositing a 0.1um thick film of a user defined material called "Nwell_Depletion" which is assigned a permittivity of 11.8 to match the permittivity of silicon. The presumption here is that the nwell is bounded by a volume p-doping concentration of approximately 1e17/cm3. Finally, the N-Well is then filled with silicon to represent the neutral region of the N-Doped well.

Including Well Capacitance in the Field Solver Parasitic Extraction

Simulating the Source/Drain diodes is the same process as the N-Well procedure described above, but with a thinner depletion insulating region of 0.02um to represent the higher doping in these regions. The depletion capacitance of the source-drain diodes is simulated by using a user defined material called "SD_Depletion" and assigning it a permittivity of 11.8. If you wish to remove this capacitance from the SPICE Netlist because it is decided to use the source/drain capacitance assigned to the active device model, then define the user defined material called "SD_Depletion", a permittivity value of say 0.1 such that the capacitance calculated will add less than 1% error to the SPICE Model Capacitance. Do not assign any insulator a permittivity of zero, as this will cause discontinuities in the field solver

Specifying Cyclical Cell Boundary Conditions for Emulating Cascaded Cells

The simulated Inverter Cell in this example is cascadable such that numerous identical cells could be cascaded together to make a ring oscillator. For this application, it is more appropriate to specify "CYCLIC" boundary conditions rather that the default "MIRROR" boundary conditions. To specify CYCLIC boundary conditions, on the Interconnect Statement, specify:


To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.

Input Files
Output Results
These examples are for reference only. Every software package contains a full set of examples suitable for that version and are installed with the software. If you see examples here that are not in your installation you should consider updating to a later version of the software.
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